/*
* hal_disp_reg.h- Sigmastar
*
* Copyright (c) [2019~2020] SigmaStar Technology.
*
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License version 2 for more details.
*
*/

#ifndef __HAL_DISP_REG_H__
#define __HAL_DISP_REG_H__

#define REG_SCL0_BASE           0x121800UL
#define REG_SCL_DMA0_BASE       0x121300UL
#define REG_SCL2_BASE           0x121A00UL
#define REG_SCL_LPLL_BASE       0x103300UL
#define REG_CHIPTOP_BASE        0x101E00UL
#define REG_SCL_CLK_BASE        0x103800UL


#ifndef REG_TABLE_END
#define REG_TABLE_END       0xFFFF
#endif

//-------------------------------------------------------------------------------------

//-------------------------------------------------------------------------------------
#define REG_CHIPTOP_00_L     (REG_CHIPTOP_BASE + 0x00)
#define REG_CHIPTOP_00_H     (REG_CHIPTOP_BASE + 0x01)
#define REG_CHIPTOP_01_L     (REG_CHIPTOP_BASE + 0x02)
#define REG_CHIPTOP_01_H     (REG_CHIPTOP_BASE + 0x03)
#define REG_CHIPTOP_02_L     (REG_CHIPTOP_BASE + 0x04)
#define REG_CHIPTOP_02_H     (REG_CHIPTOP_BASE + 0x05)
#define REG_CHIPTOP_03_L     (REG_CHIPTOP_BASE + 0x06)
#define REG_CHIPTOP_03_H     (REG_CHIPTOP_BASE + 0x07)
#define REG_CHIPTOP_04_L     (REG_CHIPTOP_BASE + 0x08)
#define REG_CHIPTOP_04_H     (REG_CHIPTOP_BASE + 0x09)
#define REG_CHIPTOP_05_L     (REG_CHIPTOP_BASE + 0x0A)
#define REG_CHIPTOP_05_H     (REG_CHIPTOP_BASE + 0x0B)
#define REG_CHIPTOP_06_L     (REG_CHIPTOP_BASE + 0x0C)
#define REG_CHIPTOP_06_H     (REG_CHIPTOP_BASE + 0x0D)
#define REG_CHIPTOP_07_L     (REG_CHIPTOP_BASE + 0x0E)
#define REG_CHIPTOP_07_H     (REG_CHIPTOP_BASE + 0x0F)
#define REG_CHIPTOP_08_L     (REG_CHIPTOP_BASE + 0x10)
#define REG_CHIPTOP_08_H     (REG_CHIPTOP_BASE + 0x11)
#define REG_CHIPTOP_09_L     (REG_CHIPTOP_BASE + 0x12)
#define REG_CHIPTOP_09_H     (REG_CHIPTOP_BASE + 0x13)
#define REG_CHIPTOP_0A_L     (REG_CHIPTOP_BASE + 0x14)
#define REG_CHIPTOP_0A_H     (REG_CHIPTOP_BASE + 0x15)
#define REG_CHIPTOP_0B_L     (REG_CHIPTOP_BASE + 0x16)
#define REG_CHIPTOP_0B_H     (REG_CHIPTOP_BASE + 0x17)
#define REG_CHIPTOP_0C_L     (REG_CHIPTOP_BASE + 0x18)
#define REG_CHIPTOP_0C_H     (REG_CHIPTOP_BASE + 0x19)
#define REG_CHIPTOP_0D_L     (REG_CHIPTOP_BASE + 0x1A)
#define REG_CHIPTOP_0D_H     (REG_CHIPTOP_BASE + 0x1B)
#define REG_CHIPTOP_0E_L     (REG_CHIPTOP_BASE + 0x1C)
#define REG_CHIPTOP_0E_H     (REG_CHIPTOP_BASE + 0x1D)
#define REG_CHIPTOP_0F_L     (REG_CHIPTOP_BASE + 0x1E)
#define REG_CHIPTOP_0F_H     (REG_CHIPTOP_BASE + 0x1F)
#define REG_CHIPTOP_10_L     (REG_CHIPTOP_BASE + 0x20)
#define REG_CHIPTOP_10_H     (REG_CHIPTOP_BASE + 0x21)
#define REG_CHIPTOP_11_L     (REG_CHIPTOP_BASE + 0x22)
#define REG_CHIPTOP_11_H     (REG_CHIPTOP_BASE + 0x23)
#define REG_CHIPTOP_12_L     (REG_CHIPTOP_BASE + 0x24)
#define REG_CHIPTOP_12_H     (REG_CHIPTOP_BASE + 0x25)
#define REG_CHIPTOP_13_L     (REG_CHIPTOP_BASE + 0x26)
#define REG_CHIPTOP_13_H     (REG_CHIPTOP_BASE + 0x27)
#define REG_CHIPTOP_14_L     (REG_CHIPTOP_BASE + 0x28)
#define REG_CHIPTOP_14_H     (REG_CHIPTOP_BASE + 0x29)
#define REG_CHIPTOP_15_L     (REG_CHIPTOP_BASE + 0x2A)
#define REG_CHIPTOP_15_H     (REG_CHIPTOP_BASE + 0x2B)
#define REG_CHIPTOP_16_L     (REG_CHIPTOP_BASE + 0x2C)
#define REG_CHIPTOP_16_H     (REG_CHIPTOP_BASE + 0x2D)
#define REG_CHIPTOP_17_L     (REG_CHIPTOP_BASE + 0x2E)
#define REG_CHIPTOP_17_H     (REG_CHIPTOP_BASE + 0x2F)
#define REG_CHIPTOP_18_L     (REG_CHIPTOP_BASE + 0x30)
#define REG_CHIPTOP_18_H     (REG_CHIPTOP_BASE + 0x31)
#define REG_CHIPTOP_19_L     (REG_CHIPTOP_BASE + 0x32)
#define REG_CHIPTOP_19_H     (REG_CHIPTOP_BASE + 0x33)
#define REG_CHIPTOP_1A_L     (REG_CHIPTOP_BASE + 0x34)
#define REG_CHIPTOP_1A_H     (REG_CHIPTOP_BASE + 0x35)
#define REG_CHIPTOP_1B_L     (REG_CHIPTOP_BASE + 0x36)
#define REG_CHIPTOP_1B_H     (REG_CHIPTOP_BASE + 0x37)
#define REG_CHIPTOP_1C_L     (REG_CHIPTOP_BASE + 0x38)
#define REG_CHIPTOP_1C_H     (REG_CHIPTOP_BASE + 0x39)
#define REG_CHIPTOP_1D_L     (REG_CHIPTOP_BASE + 0x3A)
#define REG_CHIPTOP_1D_H     (REG_CHIPTOP_BASE + 0x3B)
#define REG_CHIPTOP_1E_L     (REG_CHIPTOP_BASE + 0x3C)
#define REG_CHIPTOP_1E_H     (REG_CHIPTOP_BASE + 0x3D)
#define REG_CHIPTOP_1F_L     (REG_CHIPTOP_BASE + 0x3E)
#define REG_CHIPTOP_1F_H     (REG_CHIPTOP_BASE + 0x3F)
#define REG_CHIPTOP_20_L     (REG_CHIPTOP_BASE + 0x40)
#define REG_CHIPTOP_20_H     (REG_CHIPTOP_BASE + 0x41)
#define REG_CHIPTOP_21_L     (REG_CHIPTOP_BASE + 0x42)
#define REG_CHIPTOP_21_H     (REG_CHIPTOP_BASE + 0x43)
#define REG_CHIPTOP_22_L     (REG_CHIPTOP_BASE + 0x44)
#define REG_CHIPTOP_22_H     (REG_CHIPTOP_BASE + 0x45)
#define REG_CHIPTOP_23_L     (REG_CHIPTOP_BASE + 0x46)
#define REG_CHIPTOP_23_H     (REG_CHIPTOP_BASE + 0x47)
#define REG_CHIPTOP_24_L     (REG_CHIPTOP_BASE + 0x48)
#define REG_CHIPTOP_24_H     (REG_CHIPTOP_BASE + 0x49)
#define REG_CHIPTOP_25_L     (REG_CHIPTOP_BASE + 0x4A)
#define REG_CHIPTOP_25_H     (REG_CHIPTOP_BASE + 0x4B)
#define REG_CHIPTOP_26_L     (REG_CHIPTOP_BASE + 0x4C)
#define REG_CHIPTOP_26_H     (REG_CHIPTOP_BASE + 0x4D)
#define REG_CHIPTOP_27_L     (REG_CHIPTOP_BASE + 0x4E)
#define REG_CHIPTOP_27_H     (REG_CHIPTOP_BASE + 0x4F)
#define REG_CHIPTOP_28_L     (REG_CHIPTOP_BASE + 0x50)
#define REG_CHIPTOP_28_H     (REG_CHIPTOP_BASE + 0x51)
#define REG_CHIPTOP_29_L     (REG_CHIPTOP_BASE + 0x52)
#define REG_CHIPTOP_29_H     (REG_CHIPTOP_BASE + 0x53)
#define REG_CHIPTOP_2A_L     (REG_CHIPTOP_BASE + 0x54)
#define REG_CHIPTOP_2A_H     (REG_CHIPTOP_BASE + 0x55)
#define REG_CHIPTOP_2B_L     (REG_CHIPTOP_BASE + 0x56)
#define REG_CHIPTOP_2B_H     (REG_CHIPTOP_BASE + 0x57)
#define REG_CHIPTOP_2C_L     (REG_CHIPTOP_BASE + 0x58)
#define REG_CHIPTOP_2C_H     (REG_CHIPTOP_BASE + 0x59)
#define REG_CHIPTOP_2D_L     (REG_CHIPTOP_BASE + 0x5A)
#define REG_CHIPTOP_2D_H     (REG_CHIPTOP_BASE + 0x5B)
#define REG_CHIPTOP_2E_L     (REG_CHIPTOP_BASE + 0x5C)
#define REG_CHIPTOP_2E_H     (REG_CHIPTOP_BASE + 0x5D)
#define REG_CHIPTOP_2F_L     (REG_CHIPTOP_BASE + 0x5E)
#define REG_CHIPTOP_2F_H     (REG_CHIPTOP_BASE + 0x5F)
#define REG_CHIPTOP_30_L     (REG_CHIPTOP_BASE + 0x60)
#define REG_CHIPTOP_30_H     (REG_CHIPTOP_BASE + 0x61)
#define REG_CHIPTOP_31_L     (REG_CHIPTOP_BASE + 0x62)
#define REG_CHIPTOP_31_H     (REG_CHIPTOP_BASE + 0x63)
#define REG_CHIPTOP_32_L     (REG_CHIPTOP_BASE + 0x64)
#define REG_CHIPTOP_32_H     (REG_CHIPTOP_BASE + 0x65)
#define REG_CHIPTOP_33_L     (REG_CHIPTOP_BASE + 0x66)
#define REG_CHIPTOP_33_H     (REG_CHIPTOP_BASE + 0x67)
#define REG_CHIPTOP_34_L     (REG_CHIPTOP_BASE + 0x68)
#define REG_CHIPTOP_34_H     (REG_CHIPTOP_BASE + 0x69)
#define REG_CHIPTOP_35_L     (REG_CHIPTOP_BASE + 0x6A)
#define REG_CHIPTOP_35_H     (REG_CHIPTOP_BASE + 0x6B)
#define REG_CHIPTOP_36_L     (REG_CHIPTOP_BASE + 0x6C)
#define REG_CHIPTOP_36_H     (REG_CHIPTOP_BASE + 0x6D)
#define REG_CHIPTOP_37_L     (REG_CHIPTOP_BASE + 0x6E)
#define REG_CHIPTOP_37_H     (REG_CHIPTOP_BASE + 0x6F)
#define REG_CHIPTOP_38_L     (REG_CHIPTOP_BASE + 0x70)
#define REG_CHIPTOP_38_H     (REG_CHIPTOP_BASE + 0x71)
#define REG_CHIPTOP_39_L     (REG_CHIPTOP_BASE + 0x72)
#define REG_CHIPTOP_39_H     (REG_CHIPTOP_BASE + 0x73)
#define REG_CHIPTOP_3A_L     (REG_CHIPTOP_BASE + 0x74)
#define REG_CHIPTOP_3A_H     (REG_CHIPTOP_BASE + 0x75)
#define REG_CHIPTOP_3B_L     (REG_CHIPTOP_BASE + 0x76)
#define REG_CHIPTOP_3B_H     (REG_CHIPTOP_BASE + 0x77)
#define REG_CHIPTOP_3C_L     (REG_CHIPTOP_BASE + 0x78)
#define REG_CHIPTOP_3C_H     (REG_CHIPTOP_BASE + 0x79)
#define REG_CHIPTOP_3D_L     (REG_CHIPTOP_BASE + 0x7A)
#define REG_CHIPTOP_3D_H     (REG_CHIPTOP_BASE + 0x7B)
#define REG_CHIPTOP_3E_L     (REG_CHIPTOP_BASE + 0x7C)
#define REG_CHIPTOP_3E_H     (REG_CHIPTOP_BASE + 0x7D)
#define REG_CHIPTOP_3F_L     (REG_CHIPTOP_BASE + 0x7E)
#define REG_CHIPTOP_3F_H     (REG_CHIPTOP_BASE + 0x7F)
#define REG_CHIPTOP_40_L     (REG_CHIPTOP_BASE + 0x80)
#define REG_CHIPTOP_40_H     (REG_CHIPTOP_BASE + 0x81)
#define REG_CHIPTOP_41_L     (REG_CHIPTOP_BASE + 0x82)
#define REG_CHIPTOP_41_H     (REG_CHIPTOP_BASE + 0x83)
#define REG_CHIPTOP_42_L     (REG_CHIPTOP_BASE + 0x84)
#define REG_CHIPTOP_42_H     (REG_CHIPTOP_BASE + 0x85)
#define REG_CHIPTOP_43_L     (REG_CHIPTOP_BASE + 0x86)
#define REG_CHIPTOP_43_H     (REG_CHIPTOP_BASE + 0x87)
#define REG_CHIPTOP_44_L     (REG_CHIPTOP_BASE + 0x88)
#define REG_CHIPTOP_44_H     (REG_CHIPTOP_BASE + 0x89)
#define REG_CHIPTOP_45_L     (REG_CHIPTOP_BASE + 0x8A)
#define REG_CHIPTOP_45_H     (REG_CHIPTOP_BASE + 0x8B)
#define REG_CHIPTOP_46_L     (REG_CHIPTOP_BASE + 0x8C)
#define REG_CHIPTOP_46_H     (REG_CHIPTOP_BASE + 0x8D)
#define REG_CHIPTOP_47_L     (REG_CHIPTOP_BASE + 0x8E)
#define REG_CHIPTOP_47_H     (REG_CHIPTOP_BASE + 0x8F)
#define REG_CHIPTOP_48_L     (REG_CHIPTOP_BASE + 0x90)
#define REG_CHIPTOP_48_H     (REG_CHIPTOP_BASE + 0x91)
#define REG_CHIPTOP_49_L     (REG_CHIPTOP_BASE + 0x92)
#define REG_CHIPTOP_49_H     (REG_CHIPTOP_BASE + 0x93)
#define REG_CHIPTOP_4A_L     (REG_CHIPTOP_BASE + 0x94)
#define REG_CHIPTOP_4A_H     (REG_CHIPTOP_BASE + 0x95)
#define REG_CHIPTOP_4B_L     (REG_CHIPTOP_BASE + 0x96)
#define REG_CHIPTOP_4B_H     (REG_CHIPTOP_BASE + 0x97)
#define REG_CHIPTOP_4C_L     (REG_CHIPTOP_BASE + 0x98)
#define REG_CHIPTOP_4C_H     (REG_CHIPTOP_BASE + 0x99)
#define REG_CHIPTOP_4D_L     (REG_CHIPTOP_BASE + 0x9A)
#define REG_CHIPTOP_4D_H     (REG_CHIPTOP_BASE + 0x9B)
#define REG_CHIPTOP_4E_L     (REG_CHIPTOP_BASE + 0x9C)
#define REG_CHIPTOP_4E_H     (REG_CHIPTOP_BASE + 0x9D)
#define REG_CHIPTOP_4F_L     (REG_CHIPTOP_BASE + 0x9E)
#define REG_CHIPTOP_4F_H     (REG_CHIPTOP_BASE + 0x9F)
#define REG_CHIPTOP_50_L     (REG_CHIPTOP_BASE + 0xA0)
#define REG_CHIPTOP_50_H     (REG_CHIPTOP_BASE + 0xA1)
#define REG_CHIPTOP_51_L     (REG_CHIPTOP_BASE + 0xA2)
#define REG_CHIPTOP_51_H     (REG_CHIPTOP_BASE + 0xA3)
#define REG_CHIPTOP_52_L     (REG_CHIPTOP_BASE + 0xA4)
#define REG_CHIPTOP_52_H     (REG_CHIPTOP_BASE + 0xA5)
#define REG_CHIPTOP_53_L     (REG_CHIPTOP_BASE + 0xA6)
#define REG_CHIPTOP_53_H     (REG_CHIPTOP_BASE + 0xA7)
#define REG_CHIPTOP_54_L     (REG_CHIPTOP_BASE + 0xA8)
#define REG_CHIPTOP_54_H     (REG_CHIPTOP_BASE + 0xA9)
#define REG_CHIPTOP_55_L     (REG_CHIPTOP_BASE + 0xAA)
#define REG_CHIPTOP_55_H     (REG_CHIPTOP_BASE + 0xAB)
#define REG_CHIPTOP_56_L     (REG_CHIPTOP_BASE + 0xAC)
#define REG_CHIPTOP_56_H     (REG_CHIPTOP_BASE + 0xAD)
#define REG_CHIPTOP_57_L     (REG_CHIPTOP_BASE + 0xAE)
#define REG_CHIPTOP_57_H     (REG_CHIPTOP_BASE + 0xAF)
#define REG_CHIPTOP_58_L     (REG_CHIPTOP_BASE + 0xB0)
#define REG_CHIPTOP_58_H     (REG_CHIPTOP_BASE + 0xB1)
#define REG_CHIPTOP_59_L     (REG_CHIPTOP_BASE + 0xB2)
#define REG_CHIPTOP_59_H     (REG_CHIPTOP_BASE + 0xB3)
#define REG_CHIPTOP_5A_L     (REG_CHIPTOP_BASE + 0xB4)
#define REG_CHIPTOP_5A_H     (REG_CHIPTOP_BASE + 0xB5)
#define REG_CHIPTOP_5B_L     (REG_CHIPTOP_BASE + 0xB6)
#define REG_CHIPTOP_5B_H     (REG_CHIPTOP_BASE + 0xB7)
#define REG_CHIPTOP_5C_L     (REG_CHIPTOP_BASE + 0xB8)
#define REG_CHIPTOP_5C_H     (REG_CHIPTOP_BASE + 0xB9)
#define REG_CHIPTOP_5D_L     (REG_CHIPTOP_BASE + 0xBA)
#define REG_CHIPTOP_5D_H     (REG_CHIPTOP_BASE + 0xBB)
#define REG_CHIPTOP_5E_L     (REG_CHIPTOP_BASE + 0xBC)
#define REG_CHIPTOP_5E_H     (REG_CHIPTOP_BASE + 0xBD)
#define REG_CHIPTOP_5F_L     (REG_CHIPTOP_BASE + 0xBE)
#define REG_CHIPTOP_5F_H     (REG_CHIPTOP_BASE + 0xBF)
#define REG_CHIPTOP_60_L     (REG_CHIPTOP_BASE + 0xC0)
#define REG_CHIPTOP_60_H     (REG_CHIPTOP_BASE + 0xC1)
#define REG_CHIPTOP_61_L     (REG_CHIPTOP_BASE + 0xC2)
#define REG_CHIPTOP_61_H     (REG_CHIPTOP_BASE + 0xC3)
#define REG_CHIPTOP_62_L     (REG_CHIPTOP_BASE + 0xC4)
#define REG_CHIPTOP_62_H     (REG_CHIPTOP_BASE + 0xC5)
#define REG_CHIPTOP_63_L     (REG_CHIPTOP_BASE + 0xC6)
#define REG_CHIPTOP_63_H     (REG_CHIPTOP_BASE + 0xC7)
#define REG_CHIPTOP_64_L     (REG_CHIPTOP_BASE + 0xC8)
#define REG_CHIPTOP_64_H     (REG_CHIPTOP_BASE + 0xC9)
#define REG_CHIPTOP_65_L     (REG_CHIPTOP_BASE + 0xCA)
#define REG_CHIPTOP_65_H     (REG_CHIPTOP_BASE + 0xCB)
#define REG_CHIPTOP_66_L     (REG_CHIPTOP_BASE + 0xCC)
#define REG_CHIPTOP_66_H     (REG_CHIPTOP_BASE + 0xCD)
#define REG_CHIPTOP_67_L     (REG_CHIPTOP_BASE + 0xCE)
#define REG_CHIPTOP_67_H     (REG_CHIPTOP_BASE + 0xCF)
#define REG_CHIPTOP_68_L     (REG_CHIPTOP_BASE + 0xD0)
#define REG_CHIPTOP_68_H     (REG_CHIPTOP_BASE + 0xD1)
#define REG_CHIPTOP_69_L     (REG_CHIPTOP_BASE + 0xD2)
#define REG_CHIPTOP_69_H     (REG_CHIPTOP_BASE + 0xD3)
#define REG_CHIPTOP_6A_L     (REG_CHIPTOP_BASE + 0xD4)
#define REG_CHIPTOP_6A_H     (REG_CHIPTOP_BASE + 0xD5)
#define REG_CHIPTOP_6B_L     (REG_CHIPTOP_BASE + 0xD6)
#define REG_CHIPTOP_6B_H     (REG_CHIPTOP_BASE + 0xD7)
#define REG_CHIPTOP_6C_L     (REG_CHIPTOP_BASE + 0xD8)
#define REG_CHIPTOP_6C_H     (REG_CHIPTOP_BASE + 0xD9)
#define REG_CHIPTOP_6D_L     (REG_CHIPTOP_BASE + 0xDA)
#define REG_CHIPTOP_6D_H     (REG_CHIPTOP_BASE + 0xDB)
#define REG_CHIPTOP_6E_L     (REG_CHIPTOP_BASE + 0xDC)
#define REG_CHIPTOP_6E_H     (REG_CHIPTOP_BASE + 0xDD)
#define REG_CHIPTOP_6F_L     (REG_CHIPTOP_BASE + 0xDE)
#define REG_CHIPTOP_6F_H     (REG_CHIPTOP_BASE + 0xDF)
#define REG_CHIPTOP_70_L     (REG_CHIPTOP_BASE + 0xE0)
#define REG_CHIPTOP_70_H     (REG_CHIPTOP_BASE + 0xE1)
#define REG_CHIPTOP_71_L     (REG_CHIPTOP_BASE + 0xE2)
#define REG_CHIPTOP_71_H     (REG_CHIPTOP_BASE + 0xE3)
#define REG_CHIPTOP_72_L     (REG_CHIPTOP_BASE + 0xE4)
#define REG_CHIPTOP_72_H     (REG_CHIPTOP_BASE + 0xE5)
#define REG_CHIPTOP_73_L     (REG_CHIPTOP_BASE + 0xE6)
#define REG_CHIPTOP_73_H     (REG_CHIPTOP_BASE + 0xE7)
#define REG_CHIPTOP_74_L     (REG_CHIPTOP_BASE + 0xE8)
#define REG_CHIPTOP_74_H     (REG_CHIPTOP_BASE + 0xE9)
#define REG_CHIPTOP_75_L     (REG_CHIPTOP_BASE + 0xEA)
#define REG_CHIPTOP_75_H     (REG_CHIPTOP_BASE + 0xEB)
#define REG_CHIPTOP_76_L     (REG_CHIPTOP_BASE + 0xEC)
#define REG_CHIPTOP_76_H     (REG_CHIPTOP_BASE + 0xED)
#define REG_CHIPTOP_77_L     (REG_CHIPTOP_BASE + 0xEE)
#define REG_CHIPTOP_77_H     (REG_CHIPTOP_BASE + 0xEF)
#define REG_CHIPTOP_78_L     (REG_CHIPTOP_BASE + 0xF0)
#define REG_CHIPTOP_78_H     (REG_CHIPTOP_BASE + 0xF1)
#define REG_CHIPTOP_79_L     (REG_CHIPTOP_BASE + 0xF2)
#define REG_CHIPTOP_79_H     (REG_CHIPTOP_BASE + 0xF3)
#define REG_CHIPTOP_7A_L     (REG_CHIPTOP_BASE + 0xF4)
#define REG_CHIPTOP_7A_H     (REG_CHIPTOP_BASE + 0xF5)
#define REG_CHIPTOP_7B_L     (REG_CHIPTOP_BASE + 0xF6)
#define REG_CHIPTOP_7B_H     (REG_CHIPTOP_BASE + 0xF7)
#define REG_CHIPTOP_7C_L     (REG_CHIPTOP_BASE + 0xF8)
#define REG_CHIPTOP_7C_H     (REG_CHIPTOP_BASE + 0xF9)
#define REG_CHIPTOP_7D_L     (REG_CHIPTOP_BASE + 0xFA)
#define REG_CHIPTOP_7D_H     (REG_CHIPTOP_BASE + 0xFB)
#define REG_CHIPTOP_7E_L     (REG_CHIPTOP_BASE + 0xFC)
#define REG_CHIPTOP_7E_H     (REG_CHIPTOP_BASE + 0xFD)
#define REG_CHIPTOP_7F_L     (REG_CHIPTOP_BASE + 0xFE)
#define REG_CHIPTOP_7F_H     (REG_CHIPTOP_BASE + 0xFF)

#define REG_SCL2_00_L        (REG_SCL2_BASE + 0x00)
#define REG_SCL2_00_H        (REG_SCL2_BASE + 0x01)
#define REG_SCL2_01_L        (REG_SCL2_BASE + 0x02)
#define REG_SCL2_01_H        (REG_SCL2_BASE + 0x03)
#define REG_SCL2_02_L        (REG_SCL2_BASE + 0x04)
#define REG_SCL2_02_H        (REG_SCL2_BASE + 0x05)
#define REG_SCL2_03_L        (REG_SCL2_BASE + 0x06)
#define REG_SCL2_03_H        (REG_SCL2_BASE + 0x07)
#define REG_SCL2_04_L        (REG_SCL2_BASE + 0x08)
#define REG_SCL2_04_H        (REG_SCL2_BASE + 0x09)
#define REG_SCL2_05_L        (REG_SCL2_BASE + 0x0A)
#define REG_SCL2_05_H        (REG_SCL2_BASE + 0x0B)
#define REG_SCL2_06_L        (REG_SCL2_BASE + 0x0C)
#define REG_SCL2_06_H        (REG_SCL2_BASE + 0x0D)
#define REG_SCL2_07_L        (REG_SCL2_BASE + 0x0E)
#define REG_SCL2_07_H        (REG_SCL2_BASE + 0x0F)
#define REG_SCL2_08_L        (REG_SCL2_BASE + 0x10)
#define REG_SCL2_08_H        (REG_SCL2_BASE + 0x11)
#define REG_SCL2_09_L        (REG_SCL2_BASE + 0x12)
#define REG_SCL2_09_H        (REG_SCL2_BASE + 0x13)
#define REG_SCL2_0A_L        (REG_SCL2_BASE + 0x14)
#define REG_SCL2_0A_H        (REG_SCL2_BASE + 0x15)
#define REG_SCL2_0B_L        (REG_SCL2_BASE + 0x16)
#define REG_SCL2_0B_H        (REG_SCL2_BASE + 0x17)
#define REG_SCL2_0C_L        (REG_SCL2_BASE + 0x18)
#define REG_SCL2_0C_H        (REG_SCL2_BASE + 0x19)
#define REG_SCL2_0D_L        (REG_SCL2_BASE + 0x1A)
#define REG_SCL2_0D_H        (REG_SCL2_BASE + 0x1B)
#define REG_SCL2_0E_L        (REG_SCL2_BASE + 0x1C)
#define REG_SCL2_0E_H        (REG_SCL2_BASE + 0x1D)
#define REG_SCL2_0F_L        (REG_SCL2_BASE + 0x1E)
#define REG_SCL2_0F_H        (REG_SCL2_BASE + 0x1F)
#define REG_SCL2_10_L        (REG_SCL2_BASE + 0x20)
#define REG_SCL2_10_H        (REG_SCL2_BASE + 0x21)
#define REG_SCL2_11_L        (REG_SCL2_BASE + 0x22)
#define REG_SCL2_11_H        (REG_SCL2_BASE + 0x23)
#define REG_SCL2_12_L        (REG_SCL2_BASE + 0x24)
#define REG_SCL2_12_H        (REG_SCL2_BASE + 0x25)
#define REG_SCL2_13_L        (REG_SCL2_BASE + 0x26)
#define REG_SCL2_13_H        (REG_SCL2_BASE + 0x27)
#define REG_SCL2_14_L        (REG_SCL2_BASE + 0x28)
#define REG_SCL2_14_H        (REG_SCL2_BASE + 0x29)
#define REG_SCL2_15_L        (REG_SCL2_BASE + 0x2A)
#define REG_SCL2_15_H        (REG_SCL2_BASE + 0x2B)
#define REG_SCL2_16_L        (REG_SCL2_BASE + 0x2C)
#define REG_SCL2_16_H        (REG_SCL2_BASE + 0x2D)
#define REG_SCL2_17_L        (REG_SCL2_BASE + 0x2E)
#define REG_SCL2_17_H        (REG_SCL2_BASE + 0x2F)
#define REG_SCL2_18_L        (REG_SCL2_BASE + 0x30)
#define REG_SCL2_18_H        (REG_SCL2_BASE + 0x31)
#define REG_SCL2_19_L        (REG_SCL2_BASE + 0x32)
#define REG_SCL2_19_H        (REG_SCL2_BASE + 0x33)
#define REG_SCL2_1A_L        (REG_SCL2_BASE + 0x34)
#define REG_SCL2_1A_H        (REG_SCL2_BASE + 0x35)
#define REG_SCL2_1B_L        (REG_SCL2_BASE + 0x36)
#define REG_SCL2_1B_H        (REG_SCL2_BASE + 0x37)
#define REG_SCL2_1C_L        (REG_SCL2_BASE + 0x38)
#define REG_SCL2_1C_H        (REG_SCL2_BASE + 0x39)
#define REG_SCL2_1D_L        (REG_SCL2_BASE + 0x3A)
#define REG_SCL2_1D_H        (REG_SCL2_BASE + 0x3B)
#define REG_SCL2_1E_L        (REG_SCL2_BASE + 0x3C)
#define REG_SCL2_1E_H        (REG_SCL2_BASE + 0x3D)
#define REG_SCL2_1F_L        (REG_SCL2_BASE + 0x3E)
#define REG_SCL2_1F_H        (REG_SCL2_BASE + 0x3F)
#define REG_SCL2_20_L        (REG_SCL2_BASE + 0x40)
#define REG_SCL2_20_H        (REG_SCL2_BASE + 0x41)
#define REG_SCL2_21_L        (REG_SCL2_BASE + 0x42)
#define REG_SCL2_21_H        (REG_SCL2_BASE + 0x43)
#define REG_SCL2_22_L        (REG_SCL2_BASE + 0x44)
#define REG_SCL2_22_H        (REG_SCL2_BASE + 0x45)
#define REG_SCL2_23_L        (REG_SCL2_BASE + 0x46)
#define REG_SCL2_23_H        (REG_SCL2_BASE + 0x47)
#define REG_SCL2_24_L        (REG_SCL2_BASE + 0x48)
#define REG_SCL2_24_H        (REG_SCL2_BASE + 0x49)
#define REG_SCL2_25_L        (REG_SCL2_BASE + 0x4A)
#define REG_SCL2_25_H        (REG_SCL2_BASE + 0x4B)
#define REG_SCL2_26_L        (REG_SCL2_BASE + 0x4C)
#define REG_SCL2_26_H        (REG_SCL2_BASE + 0x4D)
#define REG_SCL2_27_L        (REG_SCL2_BASE + 0x4E)
#define REG_SCL2_27_H        (REG_SCL2_BASE + 0x4F)
#define REG_SCL2_28_L        (REG_SCL2_BASE + 0x50)
#define REG_SCL2_28_H        (REG_SCL2_BASE + 0x51)
#define REG_SCL2_29_L        (REG_SCL2_BASE + 0x52)
#define REG_SCL2_29_H        (REG_SCL2_BASE + 0x53)
#define REG_SCL2_2A_L        (REG_SCL2_BASE + 0x54)
#define REG_SCL2_2A_H        (REG_SCL2_BASE + 0x55)
#define REG_SCL2_2B_L        (REG_SCL2_BASE + 0x56)
#define REG_SCL2_2B_H        (REG_SCL2_BASE + 0x57)
#define REG_SCL2_2C_L        (REG_SCL2_BASE + 0x58)
#define REG_SCL2_2C_H        (REG_SCL2_BASE + 0x59)
#define REG_SCL2_2D_L        (REG_SCL2_BASE + 0x5A)
#define REG_SCL2_2D_H        (REG_SCL2_BASE + 0x5B)
#define REG_SCL2_2E_L        (REG_SCL2_BASE + 0x5C)
#define REG_SCL2_2E_H        (REG_SCL2_BASE + 0x5D)
#define REG_SCL2_2F_L        (REG_SCL2_BASE + 0x5E)
#define REG_SCL2_2F_H        (REG_SCL2_BASE + 0x5F)
#define REG_SCL2_30_L        (REG_SCL2_BASE + 0x60)
#define REG_SCL2_30_H        (REG_SCL2_BASE + 0x61)
#define REG_SCL2_31_L        (REG_SCL2_BASE + 0x62)
#define REG_SCL2_31_H        (REG_SCL2_BASE + 0x63)
#define REG_SCL2_32_L        (REG_SCL2_BASE + 0x64)
#define REG_SCL2_32_H        (REG_SCL2_BASE + 0x65)
#define REG_SCL2_33_L        (REG_SCL2_BASE + 0x66)
#define REG_SCL2_33_H        (REG_SCL2_BASE + 0x67)
#define REG_SCL2_34_L        (REG_SCL2_BASE + 0x68)
#define REG_SCL2_34_H        (REG_SCL2_BASE + 0x69)
#define REG_SCL2_35_L        (REG_SCL2_BASE + 0x6A)
#define REG_SCL2_35_H        (REG_SCL2_BASE + 0x6B)
#define REG_SCL2_36_L        (REG_SCL2_BASE + 0x6C)
#define REG_SCL2_36_H        (REG_SCL2_BASE + 0x6D)
#define REG_SCL2_37_L        (REG_SCL2_BASE + 0x6E)
#define REG_SCL2_37_H        (REG_SCL2_BASE + 0x6F)
#define REG_SCL2_38_L        (REG_SCL2_BASE + 0x70)
#define REG_SCL2_38_H        (REG_SCL2_BASE + 0x71)
#define REG_SCL2_39_L        (REG_SCL2_BASE + 0x72)
#define REG_SCL2_39_H        (REG_SCL2_BASE + 0x73)
#define REG_SCL2_3A_L        (REG_SCL2_BASE + 0x74)
#define REG_SCL2_3A_H        (REG_SCL2_BASE + 0x75)
#define REG_SCL2_3B_L        (REG_SCL2_BASE + 0x76)
#define REG_SCL2_3B_H        (REG_SCL2_BASE + 0x77)
#define REG_SCL2_3C_L        (REG_SCL2_BASE + 0x78)
#define REG_SCL2_3C_H        (REG_SCL2_BASE + 0x79)
#define REG_SCL2_3D_L        (REG_SCL2_BASE + 0x7A)
#define REG_SCL2_3D_H        (REG_SCL2_BASE + 0x7B)
#define REG_SCL2_3E_L        (REG_SCL2_BASE + 0x7C)
#define REG_SCL2_3E_H        (REG_SCL2_BASE + 0x7D)
#define REG_SCL2_3F_L        (REG_SCL2_BASE + 0x7E)
#define REG_SCL2_3F_H        (REG_SCL2_BASE + 0x7F)
#define REG_SCL2_40_L        (REG_SCL2_BASE + 0x80)
#define REG_SCL2_40_H        (REG_SCL2_BASE + 0x81)
#define REG_SCL2_41_L        (REG_SCL2_BASE + 0x82)
#define REG_SCL2_41_H        (REG_SCL2_BASE + 0x83)
#define REG_SCL2_42_L        (REG_SCL2_BASE + 0x84)
#define REG_SCL2_42_H        (REG_SCL2_BASE + 0x85)
#define REG_SCL2_43_L        (REG_SCL2_BASE + 0x86)
#define REG_SCL2_43_H        (REG_SCL2_BASE + 0x87)
#define REG_SCL2_44_L        (REG_SCL2_BASE + 0x88)
#define REG_SCL2_44_H        (REG_SCL2_BASE + 0x89)
#define REG_SCL2_45_L        (REG_SCL2_BASE + 0x8A)
#define REG_SCL2_45_H        (REG_SCL2_BASE + 0x8B)
#define REG_SCL2_46_L        (REG_SCL2_BASE + 0x8C)
#define REG_SCL2_46_H        (REG_SCL2_BASE + 0x8D)
#define REG_SCL2_47_L        (REG_SCL2_BASE + 0x8E)
#define REG_SCL2_47_H        (REG_SCL2_BASE + 0x8F)
#define REG_SCL2_48_L        (REG_SCL2_BASE + 0x90)
#define REG_SCL2_48_H        (REG_SCL2_BASE + 0x91)
#define REG_SCL2_49_L        (REG_SCL2_BASE + 0x92)
#define REG_SCL2_49_H        (REG_SCL2_BASE + 0x93)
#define REG_SCL2_4A_L        (REG_SCL2_BASE + 0x94)
#define REG_SCL2_4A_H        (REG_SCL2_BASE + 0x95)
#define REG_SCL2_4B_L        (REG_SCL2_BASE + 0x96)
#define REG_SCL2_4B_H        (REG_SCL2_BASE + 0x97)
#define REG_SCL2_4C_L        (REG_SCL2_BASE + 0x98)
#define REG_SCL2_4C_H        (REG_SCL2_BASE + 0x99)
#define REG_SCL2_4D_L        (REG_SCL2_BASE + 0x9A)
#define REG_SCL2_4D_H        (REG_SCL2_BASE + 0x9B)
#define REG_SCL2_4E_L        (REG_SCL2_BASE + 0x9C)
#define REG_SCL2_4E_H        (REG_SCL2_BASE + 0x9D)
#define REG_SCL2_4F_L        (REG_SCL2_BASE + 0x9E)
#define REG_SCL2_4F_H        (REG_SCL2_BASE + 0x9F)
#define REG_SCL2_50_L        (REG_SCL2_BASE + 0xA0)
#define REG_SCL2_50_H        (REG_SCL2_BASE + 0xA1)
#define REG_SCL2_51_L        (REG_SCL2_BASE + 0xA2)
#define REG_SCL2_51_H        (REG_SCL2_BASE + 0xA3)
#define REG_SCL2_52_L        (REG_SCL2_BASE + 0xA4)
#define REG_SCL2_52_H        (REG_SCL2_BASE + 0xA5)
#define REG_SCL2_53_L        (REG_SCL2_BASE + 0xA6)
#define REG_SCL2_53_H        (REG_SCL2_BASE + 0xA7)
#define REG_SCL2_54_L        (REG_SCL2_BASE + 0xA8)
#define REG_SCL2_54_H        (REG_SCL2_BASE + 0xA9)
#define REG_SCL2_55_L        (REG_SCL2_BASE + 0xAA)
#define REG_SCL2_55_H        (REG_SCL2_BASE + 0xAB)
#define REG_SCL2_56_L        (REG_SCL2_BASE + 0xAC)
#define REG_SCL2_56_H        (REG_SCL2_BASE + 0xAD)
#define REG_SCL2_57_L        (REG_SCL2_BASE + 0xAE)
#define REG_SCL2_57_H        (REG_SCL2_BASE + 0xAF)
#define REG_SCL2_58_L        (REG_SCL2_BASE + 0xB0)
#define REG_SCL2_58_H        (REG_SCL2_BASE + 0xB1)
#define REG_SCL2_59_L        (REG_SCL2_BASE + 0xB2)
#define REG_SCL2_59_H        (REG_SCL2_BASE + 0xB3)
#define REG_SCL2_5A_L        (REG_SCL2_BASE + 0xB4)
#define REG_SCL2_5A_H        (REG_SCL2_BASE + 0xB5)
#define REG_SCL2_5B_L        (REG_SCL2_BASE + 0xB6)
#define REG_SCL2_5B_H        (REG_SCL2_BASE + 0xB7)
#define REG_SCL2_5C_L        (REG_SCL2_BASE + 0xB8)
#define REG_SCL2_5C_H        (REG_SCL2_BASE + 0xB9)
#define REG_SCL2_5D_L        (REG_SCL2_BASE + 0xBA)
#define REG_SCL2_5D_H        (REG_SCL2_BASE + 0xBB)
#define REG_SCL2_5E_L        (REG_SCL2_BASE + 0xBC)
#define REG_SCL2_5E_H        (REG_SCL2_BASE + 0xBD)
#define REG_SCL2_5F_L        (REG_SCL2_BASE + 0xBE)
#define REG_SCL2_5F_H        (REG_SCL2_BASE + 0xBF)
#define REG_SCL2_60_L        (REG_SCL2_BASE + 0xC0)
#define REG_SCL2_60_H        (REG_SCL2_BASE + 0xC1)
#define REG_SCL2_61_L        (REG_SCL2_BASE + 0xC2)
#define REG_SCL2_61_H        (REG_SCL2_BASE + 0xC3)
#define REG_SCL2_62_L        (REG_SCL2_BASE + 0xC4)
#define REG_SCL2_62_H        (REG_SCL2_BASE + 0xC5)
#define REG_SCL2_63_L        (REG_SCL2_BASE + 0xC6)
#define REG_SCL2_63_H        (REG_SCL2_BASE + 0xC7)
#define REG_SCL2_64_L        (REG_SCL2_BASE + 0xC8)
#define REG_SCL2_64_H        (REG_SCL2_BASE + 0xC9)
#define REG_SCL2_65_L        (REG_SCL2_BASE + 0xCA)
#define REG_SCL2_65_H        (REG_SCL2_BASE + 0xCB)
#define REG_SCL2_66_L        (REG_SCL2_BASE + 0xCC)
#define REG_SCL2_66_H        (REG_SCL2_BASE + 0xCD)
#define REG_SCL2_67_L        (REG_SCL2_BASE + 0xCE)
#define REG_SCL2_67_H        (REG_SCL2_BASE + 0xCF)
#define REG_SCL2_68_L        (REG_SCL2_BASE + 0xD0)
#define REG_SCL2_68_H        (REG_SCL2_BASE + 0xD1)
#define REG_SCL2_69_L        (REG_SCL2_BASE + 0xD2)
#define REG_SCL2_69_H        (REG_SCL2_BASE + 0xD3)
#define REG_SCL2_6A_L        (REG_SCL2_BASE + 0xD4)
#define REG_SCL2_6A_H        (REG_SCL2_BASE + 0xD5)
#define REG_SCL2_6B_L        (REG_SCL2_BASE + 0xD6)
#define REG_SCL2_6B_H        (REG_SCL2_BASE + 0xD7)
#define REG_SCL2_6C_L        (REG_SCL2_BASE + 0xD8)
#define REG_SCL2_6C_H        (REG_SCL2_BASE + 0xD9)
#define REG_SCL2_6D_L        (REG_SCL2_BASE + 0xDA)
#define REG_SCL2_6D_H        (REG_SCL2_BASE + 0xDB)
#define REG_SCL2_6E_L        (REG_SCL2_BASE + 0xDC)
#define REG_SCL2_6E_H        (REG_SCL2_BASE + 0xDD)
#define REG_SCL2_6F_L        (REG_SCL2_BASE + 0xDE)
#define REG_SCL2_6F_H        (REG_SCL2_BASE + 0xDF)
#define REG_SCL2_70_L        (REG_SCL2_BASE + 0xE0)
#define REG_SCL2_70_H        (REG_SCL2_BASE + 0xE1)
#define REG_SCL2_71_L        (REG_SCL2_BASE + 0xE2)
#define REG_SCL2_71_H        (REG_SCL2_BASE + 0xE3)
#define REG_SCL2_72_L        (REG_SCL2_BASE + 0xE4)
#define REG_SCL2_72_H        (REG_SCL2_BASE + 0xE5)
#define REG_SCL2_73_L        (REG_SCL2_BASE + 0xE6)
#define REG_SCL2_73_H        (REG_SCL2_BASE + 0xE7)
#define REG_SCL2_74_L        (REG_SCL2_BASE + 0xE8)
#define REG_SCL2_74_H        (REG_SCL2_BASE + 0xE9)
#define REG_SCL2_75_L        (REG_SCL2_BASE + 0xEA)
#define REG_SCL2_75_H        (REG_SCL2_BASE + 0xEB)
#define REG_SCL2_76_L        (REG_SCL2_BASE + 0xEC)
#define REG_SCL2_76_H        (REG_SCL2_BASE + 0xED)
#define REG_SCL2_77_L        (REG_SCL2_BASE + 0xEE)
#define REG_SCL2_77_H        (REG_SCL2_BASE + 0xEF)
#define REG_SCL2_78_L        (REG_SCL2_BASE + 0xF0)
#define REG_SCL2_78_H        (REG_SCL2_BASE + 0xF1)
#define REG_SCL2_79_L        (REG_SCL2_BASE + 0xF2)
#define REG_SCL2_79_H        (REG_SCL2_BASE + 0xF3)
#define REG_SCL2_7A_L        (REG_SCL2_BASE + 0xF4)
#define REG_SCL2_7A_H        (REG_SCL2_BASE + 0xF5)
#define REG_SCL2_7B_L        (REG_SCL2_BASE + 0xF6)
#define REG_SCL2_7B_H        (REG_SCL2_BASE + 0xF7)
#define REG_SCL2_7C_L        (REG_SCL2_BASE + 0xF8)
#define REG_SCL2_7C_H        (REG_SCL2_BASE + 0xF9)
#define REG_SCL2_7D_L        (REG_SCL2_BASE + 0xFA)
#define REG_SCL2_7D_H        (REG_SCL2_BASE + 0xFB)
#define REG_SCL2_7E_L        (REG_SCL2_BASE + 0xFC)
#define REG_SCL2_7E_H        (REG_SCL2_BASE + 0xFD)
#define REG_SCL2_7F_L        (REG_SCL2_BASE + 0xFE)
#define REG_SCL2_7F_H        (REG_SCL2_BASE + 0xFF)


#define REG_SCL_CLK_00_L    (REG_SCL_CLK_BASE + 0x00)
#define REG_SCL_CLK_00_H    (REG_SCL_CLK_BASE + 0x01)
#define REG_SCL_CLK_01_L    (REG_SCL_CLK_BASE + 0x02)
#define REG_SCL_CLK_01_H    (REG_SCL_CLK_BASE + 0x03)
#define REG_SCL_CLK_02_L    (REG_SCL_CLK_BASE + 0x04)
#define REG_SCL_CLK_02_H    (REG_SCL_CLK_BASE + 0x05)
#define REG_SCL_CLK_03_L    (REG_SCL_CLK_BASE + 0x06)
#define REG_SCL_CLK_03_H    (REG_SCL_CLK_BASE + 0x07)
#define REG_SCL_CLK_04_L    (REG_SCL_CLK_BASE + 0x08)
#define REG_SCL_CLK_04_H    (REG_SCL_CLK_BASE + 0x09)
#define REG_SCL_CLK_05_L    (REG_SCL_CLK_BASE + 0x0A)
#define REG_SCL_CLK_05_H    (REG_SCL_CLK_BASE + 0x0B)
#define REG_SCL_CLK_06_L    (REG_SCL_CLK_BASE + 0x0C)
#define REG_SCL_CLK_06_H    (REG_SCL_CLK_BASE + 0x0D)
#define REG_SCL_CLK_07_L    (REG_SCL_CLK_BASE + 0x0E)
#define REG_SCL_CLK_07_H    (REG_SCL_CLK_BASE + 0x0F)
#define REG_SCL_CLK_08_L    (REG_SCL_CLK_BASE + 0x10)
#define REG_SCL_CLK_08_H    (REG_SCL_CLK_BASE + 0x11)
#define REG_SCL_CLK_09_L    (REG_SCL_CLK_BASE + 0x12)
#define REG_SCL_CLK_09_H    (REG_SCL_CLK_BASE + 0x13)
#define REG_SCL_CLK_0A_L    (REG_SCL_CLK_BASE + 0x14)
#define REG_SCL_CLK_0A_H    (REG_SCL_CLK_BASE + 0x15)
#define REG_SCL_CLK_0B_L    (REG_SCL_CLK_BASE + 0x16)
#define REG_SCL_CLK_0B_H    (REG_SCL_CLK_BASE + 0x17)
#define REG_SCL_CLK_0C_L    (REG_SCL_CLK_BASE + 0x18)
#define REG_SCL_CLK_0C_H    (REG_SCL_CLK_BASE + 0x19)
#define REG_SCL_CLK_0D_L    (REG_SCL_CLK_BASE + 0x1A)
#define REG_SCL_CLK_0D_H    (REG_SCL_CLK_BASE + 0x1B)
#define REG_SCL_CLK_0E_L    (REG_SCL_CLK_BASE + 0x1C)
#define REG_SCL_CLK_0E_H    (REG_SCL_CLK_BASE + 0x1D)
#define REG_SCL_CLK_0F_L    (REG_SCL_CLK_BASE + 0x1E)
#define REG_SCL_CLK_0F_H    (REG_SCL_CLK_BASE + 0x1F)
#define REG_SCL_CLK_10_L    (REG_SCL_CLK_BASE + 0x20)
#define REG_SCL_CLK_10_H    (REG_SCL_CLK_BASE + 0x21)
#define REG_SCL_CLK_11_L    (REG_SCL_CLK_BASE + 0x22)
#define REG_SCL_CLK_11_H    (REG_SCL_CLK_BASE + 0x23)
#define REG_SCL_CLK_12_L    (REG_SCL_CLK_BASE + 0x24)
#define REG_SCL_CLK_12_H    (REG_SCL_CLK_BASE + 0x25)
#define REG_SCL_CLK_13_L    (REG_SCL_CLK_BASE + 0x26)
#define REG_SCL_CLK_13_H    (REG_SCL_CLK_BASE + 0x27)
#define REG_SCL_CLK_14_L    (REG_SCL_CLK_BASE + 0x28)
#define REG_SCL_CLK_14_H    (REG_SCL_CLK_BASE + 0x29)
#define REG_SCL_CLK_15_L    (REG_SCL_CLK_BASE + 0x2A)
#define REG_SCL_CLK_15_H    (REG_SCL_CLK_BASE + 0x2B)
#define REG_SCL_CLK_16_L    (REG_SCL_CLK_BASE + 0x2C)
#define REG_SCL_CLK_16_H    (REG_SCL_CLK_BASE + 0x2D)
#define REG_SCL_CLK_17_L    (REG_SCL_CLK_BASE + 0x2E)
#define REG_SCL_CLK_17_H    (REG_SCL_CLK_BASE + 0x2F)
#define REG_SCL_CLK_18_L    (REG_SCL_CLK_BASE + 0x30)
#define REG_SCL_CLK_18_H    (REG_SCL_CLK_BASE + 0x31)
#define REG_SCL_CLK_19_L    (REG_SCL_CLK_BASE + 0x32)
#define REG_SCL_CLK_19_H    (REG_SCL_CLK_BASE + 0x33)
#define REG_SCL_CLK_1A_L    (REG_SCL_CLK_BASE + 0x34)
#define REG_SCL_CLK_1A_H    (REG_SCL_CLK_BASE + 0x35)
#define REG_SCL_CLK_1B_L    (REG_SCL_CLK_BASE + 0x36)
#define REG_SCL_CLK_1B_H    (REG_SCL_CLK_BASE + 0x37)
#define REG_SCL_CLK_1C_L    (REG_SCL_CLK_BASE + 0x38)
#define REG_SCL_CLK_1C_H    (REG_SCL_CLK_BASE + 0x39)
#define REG_SCL_CLK_1D_L    (REG_SCL_CLK_BASE + 0x3A)
#define REG_SCL_CLK_1D_H    (REG_SCL_CLK_BASE + 0x3B)
#define REG_SCL_CLK_1E_L    (REG_SCL_CLK_BASE + 0x3C)
#define REG_SCL_CLK_1E_H    (REG_SCL_CLK_BASE + 0x3D)
#define REG_SCL_CLK_1F_L    (REG_SCL_CLK_BASE + 0x3E)
#define REG_SCL_CLK_1F_H    (REG_SCL_CLK_BASE + 0x3F)
#define REG_SCL_CLK_20_L    (REG_SCL_CLK_BASE + 0x40)
#define REG_SCL_CLK_20_H    (REG_SCL_CLK_BASE + 0x41)
#define REG_SCL_CLK_21_L    (REG_SCL_CLK_BASE + 0x42)
#define REG_SCL_CLK_21_H    (REG_SCL_CLK_BASE + 0x43)
#define REG_SCL_CLK_22_L    (REG_SCL_CLK_BASE + 0x44)
#define REG_SCL_CLK_22_H    (REG_SCL_CLK_BASE + 0x45)
#define REG_SCL_CLK_23_L    (REG_SCL_CLK_BASE + 0x46)
#define REG_SCL_CLK_23_H    (REG_SCL_CLK_BASE + 0x47)
#define REG_SCL_CLK_24_L    (REG_SCL_CLK_BASE + 0x48)
#define REG_SCL_CLK_24_H    (REG_SCL_CLK_BASE + 0x49)
#define REG_SCL_CLK_25_L    (REG_SCL_CLK_BASE + 0x4A)
#define REG_SCL_CLK_25_H    (REG_SCL_CLK_BASE + 0x4B)
#define REG_SCL_CLK_26_L    (REG_SCL_CLK_BASE + 0x4C)
#define REG_SCL_CLK_26_H    (REG_SCL_CLK_BASE + 0x4D)
#define REG_SCL_CLK_27_L    (REG_SCL_CLK_BASE + 0x4E)
#define REG_SCL_CLK_27_H    (REG_SCL_CLK_BASE + 0x4F)
#define REG_SCL_CLK_28_L    (REG_SCL_CLK_BASE + 0x50)
#define REG_SCL_CLK_28_H    (REG_SCL_CLK_BASE + 0x51)
#define REG_SCL_CLK_29_L    (REG_SCL_CLK_BASE + 0x52)
#define REG_SCL_CLK_29_H    (REG_SCL_CLK_BASE + 0x53)
#define REG_SCL_CLK_2A_L    (REG_SCL_CLK_BASE + 0x54)
#define REG_SCL_CLK_2A_H    (REG_SCL_CLK_BASE + 0x55)
#define REG_SCL_CLK_2B_L    (REG_SCL_CLK_BASE + 0x56)
#define REG_SCL_CLK_2B_H    (REG_SCL_CLK_BASE + 0x57)
#define REG_SCL_CLK_2C_L    (REG_SCL_CLK_BASE + 0x58)
#define REG_SCL_CLK_2C_H    (REG_SCL_CLK_BASE + 0x59)
#define REG_SCL_CLK_2D_L    (REG_SCL_CLK_BASE + 0x5A)
#define REG_SCL_CLK_2D_H    (REG_SCL_CLK_BASE + 0x5B)
#define REG_SCL_CLK_2E_L    (REG_SCL_CLK_BASE + 0x5C)
#define REG_SCL_CLK_2E_H    (REG_SCL_CLK_BASE + 0x5D)
#define REG_SCL_CLK_2F_L    (REG_SCL_CLK_BASE + 0x5E)
#define REG_SCL_CLK_2F_H    (REG_SCL_CLK_BASE + 0x5F)
#define REG_SCL_CLK_30_L    (REG_SCL_CLK_BASE + 0x60)
#define REG_SCL_CLK_30_H    (REG_SCL_CLK_BASE + 0x61)
#define REG_SCL_CLK_31_L    (REG_SCL_CLK_BASE + 0x62)
#define REG_SCL_CLK_31_H    (REG_SCL_CLK_BASE + 0x63)
#define REG_SCL_CLK_32_L    (REG_SCL_CLK_BASE + 0x64)
#define REG_SCL_CLK_32_H    (REG_SCL_CLK_BASE + 0x65)
#define REG_SCL_CLK_33_L    (REG_SCL_CLK_BASE + 0x66)
#define REG_SCL_CLK_33_H    (REG_SCL_CLK_BASE + 0x67)
#define REG_SCL_CLK_34_L    (REG_SCL_CLK_BASE + 0x68)
#define REG_SCL_CLK_34_H    (REG_SCL_CLK_BASE + 0x69)
#define REG_SCL_CLK_35_L    (REG_SCL_CLK_BASE + 0x6A)
#define REG_SCL_CLK_35_H    (REG_SCL_CLK_BASE + 0x6B)
#define REG_SCL_CLK_36_L    (REG_SCL_CLK_BASE + 0x6C)
#define REG_SCL_CLK_36_H    (REG_SCL_CLK_BASE + 0x6D)
#define REG_SCL_CLK_37_L    (REG_SCL_CLK_BASE + 0x6E)
#define REG_SCL_CLK_37_H    (REG_SCL_CLK_BASE + 0x6F)
#define REG_SCL_CLK_38_L    (REG_SCL_CLK_BASE + 0x70)
#define REG_SCL_CLK_38_H    (REG_SCL_CLK_BASE + 0x71)
#define REG_SCL_CLK_39_L    (REG_SCL_CLK_BASE + 0x72)
#define REG_SCL_CLK_39_H    (REG_SCL_CLK_BASE + 0x73)
#define REG_SCL_CLK_3A_L    (REG_SCL_CLK_BASE + 0x74)
#define REG_SCL_CLK_3A_H    (REG_SCL_CLK_BASE + 0x75)
#define REG_SCL_CLK_3B_L    (REG_SCL_CLK_BASE + 0x76)
#define REG_SCL_CLK_3B_H    (REG_SCL_CLK_BASE + 0x77)
#define REG_SCL_CLK_3C_L    (REG_SCL_CLK_BASE + 0x78)
#define REG_SCL_CLK_3C_H    (REG_SCL_CLK_BASE + 0x79)
#define REG_SCL_CLK_3D_L    (REG_SCL_CLK_BASE + 0x7A)
#define REG_SCL_CLK_3D_H    (REG_SCL_CLK_BASE + 0x7B)
#define REG_SCL_CLK_3E_L    (REG_SCL_CLK_BASE + 0x7C)
#define REG_SCL_CLK_3E_H    (REG_SCL_CLK_BASE + 0x7D)
#define REG_SCL_CLK_3F_L    (REG_SCL_CLK_BASE + 0x7E)
#define REG_SCL_CLK_3F_H    (REG_SCL_CLK_BASE + 0x7F)
#define REG_SCL_CLK_40_L    (REG_SCL_CLK_BASE + 0x80)
#define REG_SCL_CLK_40_H    (REG_SCL_CLK_BASE + 0x81)
#define REG_SCL_CLK_41_L    (REG_SCL_CLK_BASE + 0x82)
#define REG_SCL_CLK_41_H    (REG_SCL_CLK_BASE + 0x83)
#define REG_SCL_CLK_42_L    (REG_SCL_CLK_BASE + 0x84)
#define REG_SCL_CLK_42_H    (REG_SCL_CLK_BASE + 0x85)
#define REG_SCL_CLK_43_L    (REG_SCL_CLK_BASE + 0x86)
#define REG_SCL_CLK_43_H    (REG_SCL_CLK_BASE + 0x87)
#define REG_SCL_CLK_44_L    (REG_SCL_CLK_BASE + 0x88)
#define REG_SCL_CLK_44_H    (REG_SCL_CLK_BASE + 0x89)
#define REG_SCL_CLK_45_L    (REG_SCL_CLK_BASE + 0x8A)
#define REG_SCL_CLK_45_H    (REG_SCL_CLK_BASE + 0x8B)
#define REG_SCL_CLK_46_L    (REG_SCL_CLK_BASE + 0x8C)
#define REG_SCL_CLK_46_H    (REG_SCL_CLK_BASE + 0x8D)
#define REG_SCL_CLK_47_L    (REG_SCL_CLK_BASE + 0x8E)
#define REG_SCL_CLK_47_H    (REG_SCL_CLK_BASE + 0x8F)
#define REG_SCL_CLK_48_L    (REG_SCL_CLK_BASE + 0x90)
#define REG_SCL_CLK_48_H    (REG_SCL_CLK_BASE + 0x91)
#define REG_SCL_CLK_49_L    (REG_SCL_CLK_BASE + 0x92)
#define REG_SCL_CLK_49_H    (REG_SCL_CLK_BASE + 0x93)
#define REG_SCL_CLK_4A_L    (REG_SCL_CLK_BASE + 0x94)
#define REG_SCL_CLK_4A_H    (REG_SCL_CLK_BASE + 0x95)
#define REG_SCL_CLK_4B_L    (REG_SCL_CLK_BASE + 0x96)
#define REG_SCL_CLK_4B_H    (REG_SCL_CLK_BASE + 0x97)
#define REG_SCL_CLK_4C_L    (REG_SCL_CLK_BASE + 0x98)
#define REG_SCL_CLK_4C_H    (REG_SCL_CLK_BASE + 0x99)
#define REG_SCL_CLK_4D_L    (REG_SCL_CLK_BASE + 0x9A)
#define REG_SCL_CLK_4D_H    (REG_SCL_CLK_BASE + 0x9B)
#define REG_SCL_CLK_4E_L    (REG_SCL_CLK_BASE + 0x9C)
#define REG_SCL_CLK_4E_H    (REG_SCL_CLK_BASE + 0x9D)
#define REG_SCL_CLK_4F_L    (REG_SCL_CLK_BASE + 0x9E)
#define REG_SCL_CLK_4F_H    (REG_SCL_CLK_BASE + 0x9F)
#define REG_SCL_CLK_50_L    (REG_SCL_CLK_BASE + 0xA0)
#define REG_SCL_CLK_50_H    (REG_SCL_CLK_BASE + 0xA1)
#define REG_SCL_CLK_51_L    (REG_SCL_CLK_BASE + 0xA2)
#define REG_SCL_CLK_51_H    (REG_SCL_CLK_BASE + 0xA3)
#define REG_SCL_CLK_52_L    (REG_SCL_CLK_BASE + 0xA4)
#define REG_SCL_CLK_52_H    (REG_SCL_CLK_BASE + 0xA5)
#define REG_SCL_CLK_53_L    (REG_SCL_CLK_BASE + 0xA6)
#define REG_SCL_CLK_53_H    (REG_SCL_CLK_BASE + 0xA7)
#define REG_SCL_CLK_54_L    (REG_SCL_CLK_BASE + 0xA8)
#define REG_SCL_CLK_54_H    (REG_SCL_CLK_BASE + 0xA9)
#define REG_SCL_CLK_55_L    (REG_SCL_CLK_BASE + 0xAA)
#define REG_SCL_CLK_55_H    (REG_SCL_CLK_BASE + 0xAB)
#define REG_SCL_CLK_56_L    (REG_SCL_CLK_BASE + 0xAC)
#define REG_SCL_CLK_56_H    (REG_SCL_CLK_BASE + 0xAD)
#define REG_SCL_CLK_57_L    (REG_SCL_CLK_BASE + 0xAE)
#define REG_SCL_CLK_57_H    (REG_SCL_CLK_BASE + 0xAF)
#define REG_SCL_CLK_58_L    (REG_SCL_CLK_BASE + 0xB0)
#define REG_SCL_CLK_58_H    (REG_SCL_CLK_BASE + 0xB1)
#define REG_SCL_CLK_59_L    (REG_SCL_CLK_BASE + 0xB2)
#define REG_SCL_CLK_59_H    (REG_SCL_CLK_BASE + 0xB3)
#define REG_SCL_CLK_5A_L    (REG_SCL_CLK_BASE + 0xB4)
#define REG_SCL_CLK_5A_H    (REG_SCL_CLK_BASE + 0xB5)
#define REG_SCL_CLK_5B_L    (REG_SCL_CLK_BASE + 0xB6)
#define REG_SCL_CLK_5B_H    (REG_SCL_CLK_BASE + 0xB7)
#define REG_SCL_CLK_5C_L    (REG_SCL_CLK_BASE + 0xB8)
#define REG_SCL_CLK_5C_H    (REG_SCL_CLK_BASE + 0xB9)
#define REG_SCL_CLK_5D_L    (REG_SCL_CLK_BASE + 0xBA)
#define REG_SCL_CLK_5D_H    (REG_SCL_CLK_BASE + 0xBB)
#define REG_SCL_CLK_5E_L    (REG_SCL_CLK_BASE + 0xBC)
#define REG_SCL_CLK_5E_H    (REG_SCL_CLK_BASE + 0xBD)
#define REG_SCL_CLK_5F_L    (REG_SCL_CLK_BASE + 0xBE)
#define REG_SCL_CLK_5F_H    (REG_SCL_CLK_BASE + 0xBF)
#define REG_SCL_CLK_60_L    (REG_SCL_CLK_BASE + 0xC0)
#define REG_SCL_CLK_60_H    (REG_SCL_CLK_BASE + 0xC1)
#define REG_SCL_CLK_61_L    (REG_SCL_CLK_BASE + 0xC2)
#define REG_SCL_CLK_61_H    (REG_SCL_CLK_BASE + 0xC3)
#define REG_SCL_CLK_62_L    (REG_SCL_CLK_BASE + 0xC4)
#define REG_SCL_CLK_62_H    (REG_SCL_CLK_BASE + 0xC5)
#define REG_SCL_CLK_63_L    (REG_SCL_CLK_BASE + 0xC6)
#define REG_SCL_CLK_63_H    (REG_SCL_CLK_BASE + 0xC7)
#define REG_SCL_CLK_64_L    (REG_SCL_CLK_BASE + 0xC8)
#define REG_SCL_CLK_64_H    (REG_SCL_CLK_BASE + 0xC9)
#define REG_SCL_CLK_65_L    (REG_SCL_CLK_BASE + 0xCA)
#define REG_SCL_CLK_65_H    (REG_SCL_CLK_BASE + 0xCB)
#define REG_SCL_CLK_66_L    (REG_SCL_CLK_BASE + 0xCC)
#define REG_SCL_CLK_66_H    (REG_SCL_CLK_BASE + 0xCD)
#define REG_SCL_CLK_67_L    (REG_SCL_CLK_BASE + 0xCE)
#define REG_SCL_CLK_67_H    (REG_SCL_CLK_BASE + 0xCF)
#define REG_SCL_CLK_68_L    (REG_SCL_CLK_BASE + 0xD0)
#define REG_SCL_CLK_68_H    (REG_SCL_CLK_BASE + 0xD1)
#define REG_SCL_CLK_69_L    (REG_SCL_CLK_BASE + 0xD2)
#define REG_SCL_CLK_69_H    (REG_SCL_CLK_BASE + 0xD3)
#define REG_SCL_CLK_6A_L    (REG_SCL_CLK_BASE + 0xD4)
#define REG_SCL_CLK_6A_H    (REG_SCL_CLK_BASE + 0xD5)
#define REG_SCL_CLK_6B_L    (REG_SCL_CLK_BASE + 0xD6)
#define REG_SCL_CLK_6B_H    (REG_SCL_CLK_BASE + 0xD7)
#define REG_SCL_CLK_6C_L    (REG_SCL_CLK_BASE + 0xD8)
#define REG_SCL_CLK_6C_H    (REG_SCL_CLK_BASE + 0xD9)
#define REG_SCL_CLK_6D_L    (REG_SCL_CLK_BASE + 0xDA)
#define REG_SCL_CLK_6D_H    (REG_SCL_CLK_BASE + 0xDB)
#define REG_SCL_CLK_6E_L    (REG_SCL_CLK_BASE + 0xDC)
#define REG_SCL_CLK_6E_H    (REG_SCL_CLK_BASE + 0xDD)
#define REG_SCL_CLK_6F_L    (REG_SCL_CLK_BASE + 0xDE)
#define REG_SCL_CLK_6F_H    (REG_SCL_CLK_BASE + 0xDF)
#define REG_SCL_CLK_70_L    (REG_SCL_CLK_BASE + 0xE0)
#define REG_SCL_CLK_70_H    (REG_SCL_CLK_BASE + 0xE1)
#define REG_SCL_CLK_71_L    (REG_SCL_CLK_BASE + 0xE2)
#define REG_SCL_CLK_71_H    (REG_SCL_CLK_BASE + 0xE3)
#define REG_SCL_CLK_72_L    (REG_SCL_CLK_BASE + 0xE4)
#define REG_SCL_CLK_72_H    (REG_SCL_CLK_BASE + 0xE5)
#define REG_SCL_CLK_73_L    (REG_SCL_CLK_BASE + 0xE6)
#define REG_SCL_CLK_73_H    (REG_SCL_CLK_BASE + 0xE7)
#define REG_SCL_CLK_74_L    (REG_SCL_CLK_BASE + 0xE8)
#define REG_SCL_CLK_74_H    (REG_SCL_CLK_BASE + 0xE9)
#define REG_SCL_CLK_75_L    (REG_SCL_CLK_BASE + 0xEA)
#define REG_SCL_CLK_75_H    (REG_SCL_CLK_BASE + 0xEB)
#define REG_SCL_CLK_76_L    (REG_SCL_CLK_BASE + 0xEC)
#define REG_SCL_CLK_76_H    (REG_SCL_CLK_BASE + 0xED)
#define REG_SCL_CLK_77_L    (REG_SCL_CLK_BASE + 0xEE)
#define REG_SCL_CLK_77_H    (REG_SCL_CLK_BASE + 0xEF)
#define REG_SCL_CLK_78_L    (REG_SCL_CLK_BASE + 0xF0)
#define REG_SCL_CLK_78_H    (REG_SCL_CLK_BASE + 0xF1)
#define REG_SCL_CLK_79_L    (REG_SCL_CLK_BASE + 0xF2)
#define REG_SCL_CLK_79_H    (REG_SCL_CLK_BASE + 0xF3)
#define REG_SCL_CLK_7A_L    (REG_SCL_CLK_BASE + 0xF4)
#define REG_SCL_CLK_7A_H    (REG_SCL_CLK_BASE + 0xF5)
#define REG_SCL_CLK_7B_L    (REG_SCL_CLK_BASE + 0xF6)
#define REG_SCL_CLK_7B_H    (REG_SCL_CLK_BASE + 0xF7)
#define REG_SCL_CLK_7C_L    (REG_SCL_CLK_BASE + 0xF8)
#define REG_SCL_CLK_7C_H    (REG_SCL_CLK_BASE + 0xF9)
#define REG_SCL_CLK_7D_L    (REG_SCL_CLK_BASE + 0xFA)
#define REG_SCL_CLK_7D_H    (REG_SCL_CLK_BASE + 0xFB)
#define REG_SCL_CLK_7E_L    (REG_SCL_CLK_BASE + 0xFC)
#define REG_SCL_CLK_7E_H    (REG_SCL_CLK_BASE + 0xFD)
#define REG_SCL_CLK_7F_L    (REG_SCL_CLK_BASE + 0xFE)
#define REG_SCL_CLK_7F_H    (REG_SCL_CLK_BASE + 0xFF)


#define REG_SCL_DMA0_00_L    (REG_SCL_DMA0_BASE + 0x00)
#define REG_SCL_DMA0_00_H    (REG_SCL_DMA0_BASE + 0x01)
#define REG_SCL_DMA0_01_L    (REG_SCL_DMA0_BASE + 0x02)
#define REG_SCL_DMA0_01_H    (REG_SCL_DMA0_BASE + 0x03)
#define REG_SCL_DMA0_02_L    (REG_SCL_DMA0_BASE + 0x04)
#define REG_SCL_DMA0_02_H    (REG_SCL_DMA0_BASE + 0x05)
#define REG_SCL_DMA0_03_L    (REG_SCL_DMA0_BASE + 0x06)
#define REG_SCL_DMA0_03_H    (REG_SCL_DMA0_BASE + 0x07)
#define REG_SCL_DMA0_04_L    (REG_SCL_DMA0_BASE + 0x08)
#define REG_SCL_DMA0_04_H    (REG_SCL_DMA0_BASE + 0x09)
#define REG_SCL_DMA0_05_L    (REG_SCL_DMA0_BASE + 0x0A)
#define REG_SCL_DMA0_05_H    (REG_SCL_DMA0_BASE + 0x0B)
#define REG_SCL_DMA0_06_L    (REG_SCL_DMA0_BASE + 0x0C)
#define REG_SCL_DMA0_06_H    (REG_SCL_DMA0_BASE + 0x0D)
#define REG_SCL_DMA0_07_L    (REG_SCL_DMA0_BASE + 0x0E)
#define REG_SCL_DMA0_07_H    (REG_SCL_DMA0_BASE + 0x0F)
#define REG_SCL_DMA0_08_L    (REG_SCL_DMA0_BASE + 0x10)
#define REG_SCL_DMA0_08_H    (REG_SCL_DMA0_BASE + 0x11)
#define REG_SCL_DMA0_09_L    (REG_SCL_DMA0_BASE + 0x12)
#define REG_SCL_DMA0_09_H    (REG_SCL_DMA0_BASE + 0x13)
#define REG_SCL_DMA0_0A_L    (REG_SCL_DMA0_BASE + 0x14)
#define REG_SCL_DMA0_0A_H    (REG_SCL_DMA0_BASE + 0x15)
#define REG_SCL_DMA0_0B_L    (REG_SCL_DMA0_BASE + 0x16)
#define REG_SCL_DMA0_0B_H    (REG_SCL_DMA0_BASE + 0x17)
#define REG_SCL_DMA0_0C_L    (REG_SCL_DMA0_BASE + 0x18)
#define REG_SCL_DMA0_0C_H    (REG_SCL_DMA0_BASE + 0x19)
#define REG_SCL_DMA0_0D_L    (REG_SCL_DMA0_BASE + 0x1A)
#define REG_SCL_DMA0_0D_H    (REG_SCL_DMA0_BASE + 0x1B)
#define REG_SCL_DMA0_0E_L    (REG_SCL_DMA0_BASE + 0x1C)
#define REG_SCL_DMA0_0E_H    (REG_SCL_DMA0_BASE + 0x1D)
#define REG_SCL_DMA0_0F_L    (REG_SCL_DMA0_BASE + 0x1E)
#define REG_SCL_DMA0_0F_H    (REG_SCL_DMA0_BASE + 0x1F)
#define REG_SCL_DMA0_10_L    (REG_SCL_DMA0_BASE + 0x20)
#define REG_SCL_DMA0_10_H    (REG_SCL_DMA0_BASE + 0x21)
#define REG_SCL_DMA0_11_L    (REG_SCL_DMA0_BASE + 0x22)
#define REG_SCL_DMA0_11_H    (REG_SCL_DMA0_BASE + 0x23)
#define REG_SCL_DMA0_12_L    (REG_SCL_DMA0_BASE + 0x24)
#define REG_SCL_DMA0_12_H    (REG_SCL_DMA0_BASE + 0x25)
#define REG_SCL_DMA0_13_L    (REG_SCL_DMA0_BASE + 0x26)
#define REG_SCL_DMA0_13_H    (REG_SCL_DMA0_BASE + 0x27)
#define REG_SCL_DMA0_14_L    (REG_SCL_DMA0_BASE + 0x28)
#define REG_SCL_DMA0_14_H    (REG_SCL_DMA0_BASE + 0x29)
#define REG_SCL_DMA0_15_L    (REG_SCL_DMA0_BASE + 0x2A)
#define REG_SCL_DMA0_15_H    (REG_SCL_DMA0_BASE + 0x2B)
#define REG_SCL_DMA0_16_L    (REG_SCL_DMA0_BASE + 0x2C)
#define REG_SCL_DMA0_16_H    (REG_SCL_DMA0_BASE + 0x2D)
#define REG_SCL_DMA0_17_L    (REG_SCL_DMA0_BASE + 0x2E)
#define REG_SCL_DMA0_17_H    (REG_SCL_DMA0_BASE + 0x2F)
#define REG_SCL_DMA0_18_L    (REG_SCL_DMA0_BASE + 0x30)
#define REG_SCL_DMA0_18_H    (REG_SCL_DMA0_BASE + 0x31)
#define REG_SCL_DMA0_19_L    (REG_SCL_DMA0_BASE + 0x32)
#define REG_SCL_DMA0_19_H    (REG_SCL_DMA0_BASE + 0x33)
#define REG_SCL_DMA0_1A_L    (REG_SCL_DMA0_BASE + 0x34)
#define REG_SCL_DMA0_1A_H    (REG_SCL_DMA0_BASE + 0x35)
#define REG_SCL_DMA0_1B_L    (REG_SCL_DMA0_BASE + 0x36)
#define REG_SCL_DMA0_1B_H    (REG_SCL_DMA0_BASE + 0x37)
#define REG_SCL_DMA0_1C_L    (REG_SCL_DMA0_BASE + 0x38)
#define REG_SCL_DMA0_1C_H    (REG_SCL_DMA0_BASE + 0x39)
#define REG_SCL_DMA0_1D_L    (REG_SCL_DMA0_BASE + 0x3A)
#define REG_SCL_DMA0_1D_H    (REG_SCL_DMA0_BASE + 0x3B)
#define REG_SCL_DMA0_1E_L    (REG_SCL_DMA0_BASE + 0x3C)
#define REG_SCL_DMA0_1E_H    (REG_SCL_DMA0_BASE + 0x3D)
#define REG_SCL_DMA0_1F_L    (REG_SCL_DMA0_BASE + 0x3E)
#define REG_SCL_DMA0_1F_H    (REG_SCL_DMA0_BASE + 0x3F)
#define REG_SCL_DMA0_20_L    (REG_SCL_DMA0_BASE + 0x40)
#define REG_SCL_DMA0_20_H    (REG_SCL_DMA0_BASE + 0x41)
#define REG_SCL_DMA0_21_L    (REG_SCL_DMA0_BASE + 0x42)
#define REG_SCL_DMA0_21_H    (REG_SCL_DMA0_BASE + 0x43)
#define REG_SCL_DMA0_22_L    (REG_SCL_DMA0_BASE + 0x44)
#define REG_SCL_DMA0_22_H    (REG_SCL_DMA0_BASE + 0x45)
#define REG_SCL_DMA0_23_L    (REG_SCL_DMA0_BASE + 0x46)
#define REG_SCL_DMA0_23_H    (REG_SCL_DMA0_BASE + 0x47)
#define REG_SCL_DMA0_24_L    (REG_SCL_DMA0_BASE + 0x48)
#define REG_SCL_DMA0_24_H    (REG_SCL_DMA0_BASE + 0x49)
#define REG_SCL_DMA0_25_L    (REG_SCL_DMA0_BASE + 0x4A)
#define REG_SCL_DMA0_25_H    (REG_SCL_DMA0_BASE + 0x4B)
#define REG_SCL_DMA0_26_L    (REG_SCL_DMA0_BASE + 0x4C)
#define REG_SCL_DMA0_26_H    (REG_SCL_DMA0_BASE + 0x4D)
#define REG_SCL_DMA0_27_L    (REG_SCL_DMA0_BASE + 0x4E)
#define REG_SCL_DMA0_27_H    (REG_SCL_DMA0_BASE + 0x4F)
#define REG_SCL_DMA0_28_L    (REG_SCL_DMA0_BASE + 0x50)
#define REG_SCL_DMA0_28_H    (REG_SCL_DMA0_BASE + 0x51)
#define REG_SCL_DMA0_29_L    (REG_SCL_DMA0_BASE + 0x52)
#define REG_SCL_DMA0_29_H    (REG_SCL_DMA0_BASE + 0x53)
#define REG_SCL_DMA0_2A_L    (REG_SCL_DMA0_BASE + 0x54)
#define REG_SCL_DMA0_2A_H    (REG_SCL_DMA0_BASE + 0x55)
#define REG_SCL_DMA0_2B_L    (REG_SCL_DMA0_BASE + 0x56)
#define REG_SCL_DMA0_2B_H    (REG_SCL_DMA0_BASE + 0x57)
#define REG_SCL_DMA0_2C_L    (REG_SCL_DMA0_BASE + 0x58)
#define REG_SCL_DMA0_2C_H    (REG_SCL_DMA0_BASE + 0x59)
#define REG_SCL_DMA0_2D_L    (REG_SCL_DMA0_BASE + 0x5A)
#define REG_SCL_DMA0_2D_H    (REG_SCL_DMA0_BASE + 0x5B)
#define REG_SCL_DMA0_2E_L    (REG_SCL_DMA0_BASE + 0x5C)
#define REG_SCL_DMA0_2E_H    (REG_SCL_DMA0_BASE + 0x5D)
#define REG_SCL_DMA0_2F_L    (REG_SCL_DMA0_BASE + 0x5E)
#define REG_SCL_DMA0_2F_H    (REG_SCL_DMA0_BASE + 0x5F)
#define REG_SCL_DMA0_30_L    (REG_SCL_DMA0_BASE + 0x60)
#define REG_SCL_DMA0_30_H    (REG_SCL_DMA0_BASE + 0x61)
#define REG_SCL_DMA0_31_L    (REG_SCL_DMA0_BASE + 0x62)
#define REG_SCL_DMA0_31_H    (REG_SCL_DMA0_BASE + 0x63)
#define REG_SCL_DMA0_32_L    (REG_SCL_DMA0_BASE + 0x64)
#define REG_SCL_DMA0_32_H    (REG_SCL_DMA0_BASE + 0x65)
#define REG_SCL_DMA0_33_L    (REG_SCL_DMA0_BASE + 0x66)
#define REG_SCL_DMA0_33_H    (REG_SCL_DMA0_BASE + 0x67)
#define REG_SCL_DMA0_34_L    (REG_SCL_DMA0_BASE + 0x68)
#define REG_SCL_DMA0_34_H    (REG_SCL_DMA0_BASE + 0x69)
#define REG_SCL_DMA0_35_L    (REG_SCL_DMA0_BASE + 0x6A)
#define REG_SCL_DMA0_35_H    (REG_SCL_DMA0_BASE + 0x6B)
#define REG_SCL_DMA0_36_L    (REG_SCL_DMA0_BASE + 0x6C)
#define REG_SCL_DMA0_36_H    (REG_SCL_DMA0_BASE + 0x6D)
#define REG_SCL_DMA0_37_L    (REG_SCL_DMA0_BASE + 0x6E)
#define REG_SCL_DMA0_37_H    (REG_SCL_DMA0_BASE + 0x6F)
#define REG_SCL_DMA0_38_L    (REG_SCL_DMA0_BASE + 0x70)
#define REG_SCL_DMA0_38_H    (REG_SCL_DMA0_BASE + 0x71)
#define REG_SCL_DMA0_39_L    (REG_SCL_DMA0_BASE + 0x72)
#define REG_SCL_DMA0_39_H    (REG_SCL_DMA0_BASE + 0x73)
#define REG_SCL_DMA0_3A_L    (REG_SCL_DMA0_BASE + 0x74)
#define REG_SCL_DMA0_3A_H    (REG_SCL_DMA0_BASE + 0x75)
#define REG_SCL_DMA0_3B_L    (REG_SCL_DMA0_BASE + 0x76)
#define REG_SCL_DMA0_3B_H    (REG_SCL_DMA0_BASE + 0x77)
#define REG_SCL_DMA0_3C_L    (REG_SCL_DMA0_BASE + 0x78)
#define REG_SCL_DMA0_3C_H    (REG_SCL_DMA0_BASE + 0x79)
#define REG_SCL_DMA0_3D_L    (REG_SCL_DMA0_BASE + 0x7A)
#define REG_SCL_DMA0_3D_H    (REG_SCL_DMA0_BASE + 0x7B)
#define REG_SCL_DMA0_3E_L    (REG_SCL_DMA0_BASE + 0x7C)
#define REG_SCL_DMA0_3E_H    (REG_SCL_DMA0_BASE + 0x7D)
#define REG_SCL_DMA0_3F_L    (REG_SCL_DMA0_BASE + 0x7E)
#define REG_SCL_DMA0_3F_H    (REG_SCL_DMA0_BASE + 0x7F)
#define REG_SCL_DMA0_40_L    (REG_SCL_DMA0_BASE + 0x80)
#define REG_SCL_DMA0_40_H    (REG_SCL_DMA0_BASE + 0x81)
#define REG_SCL_DMA0_41_L    (REG_SCL_DMA0_BASE + 0x82)
#define REG_SCL_DMA0_41_H    (REG_SCL_DMA0_BASE + 0x83)
#define REG_SCL_DMA0_42_L    (REG_SCL_DMA0_BASE + 0x84)
#define REG_SCL_DMA0_42_H    (REG_SCL_DMA0_BASE + 0x85)
#define REG_SCL_DMA0_43_L    (REG_SCL_DMA0_BASE + 0x86)
#define REG_SCL_DMA0_43_H    (REG_SCL_DMA0_BASE + 0x87)
#define REG_SCL_DMA0_44_L    (REG_SCL_DMA0_BASE + 0x88)
#define REG_SCL_DMA0_44_H    (REG_SCL_DMA0_BASE + 0x89)
#define REG_SCL_DMA0_45_L    (REG_SCL_DMA0_BASE + 0x8A)
#define REG_SCL_DMA0_45_H    (REG_SCL_DMA0_BASE + 0x8B)
#define REG_SCL_DMA0_46_L    (REG_SCL_DMA0_BASE + 0x8C)
#define REG_SCL_DMA0_46_H    (REG_SCL_DMA0_BASE + 0x8D)
#define REG_SCL_DMA0_47_L    (REG_SCL_DMA0_BASE + 0x8E)
#define REG_SCL_DMA0_47_H    (REG_SCL_DMA0_BASE + 0x8F)
#define REG_SCL_DMA0_48_L    (REG_SCL_DMA0_BASE + 0x90)
#define REG_SCL_DMA0_48_H    (REG_SCL_DMA0_BASE + 0x91)
#define REG_SCL_DMA0_49_L    (REG_SCL_DMA0_BASE + 0x92)
#define REG_SCL_DMA0_49_H    (REG_SCL_DMA0_BASE + 0x93)
#define REG_SCL_DMA0_4A_L    (REG_SCL_DMA0_BASE + 0x94)
#define REG_SCL_DMA0_4A_H    (REG_SCL_DMA0_BASE + 0x95)
#define REG_SCL_DMA0_4B_L    (REG_SCL_DMA0_BASE + 0x96)
#define REG_SCL_DMA0_4B_H    (REG_SCL_DMA0_BASE + 0x97)
#define REG_SCL_DMA0_4C_L    (REG_SCL_DMA0_BASE + 0x98)
#define REG_SCL_DMA0_4C_H    (REG_SCL_DMA0_BASE + 0x99)
#define REG_SCL_DMA0_4D_L    (REG_SCL_DMA0_BASE + 0x9A)
#define REG_SCL_DMA0_4D_H    (REG_SCL_DMA0_BASE + 0x9B)
#define REG_SCL_DMA0_4E_L    (REG_SCL_DMA0_BASE + 0x9C)
#define REG_SCL_DMA0_4E_H    (REG_SCL_DMA0_BASE + 0x9D)
#define REG_SCL_DMA0_4F_L    (REG_SCL_DMA0_BASE + 0x9E)
#define REG_SCL_DMA0_4F_H    (REG_SCL_DMA0_BASE + 0x9F)
#define REG_SCL_DMA0_50_L    (REG_SCL_DMA0_BASE + 0xA0)
#define REG_SCL_DMA0_50_H    (REG_SCL_DMA0_BASE + 0xA1)
#define REG_SCL_DMA0_51_L    (REG_SCL_DMA0_BASE + 0xA2)
#define REG_SCL_DMA0_51_H    (REG_SCL_DMA0_BASE + 0xA3)
#define REG_SCL_DMA0_52_L    (REG_SCL_DMA0_BASE + 0xA4)
#define REG_SCL_DMA0_52_H    (REG_SCL_DMA0_BASE + 0xA5)
#define REG_SCL_DMA0_53_L    (REG_SCL_DMA0_BASE + 0xA6)
#define REG_SCL_DMA0_53_H    (REG_SCL_DMA0_BASE + 0xA7)
#define REG_SCL_DMA0_54_L    (REG_SCL_DMA0_BASE + 0xA8)
#define REG_SCL_DMA0_54_H    (REG_SCL_DMA0_BASE + 0xA9)
#define REG_SCL_DMA0_55_L    (REG_SCL_DMA0_BASE + 0xAA)
#define REG_SCL_DMA0_55_H    (REG_SCL_DMA0_BASE + 0xAB)
#define REG_SCL_DMA0_56_L    (REG_SCL_DMA0_BASE + 0xAC)
#define REG_SCL_DMA0_56_H    (REG_SCL_DMA0_BASE + 0xAD)
#define REG_SCL_DMA0_57_L    (REG_SCL_DMA0_BASE + 0xAE)
#define REG_SCL_DMA0_57_H    (REG_SCL_DMA0_BASE + 0xAF)
#define REG_SCL_DMA0_58_L    (REG_SCL_DMA0_BASE + 0xB0)
#define REG_SCL_DMA0_58_H    (REG_SCL_DMA0_BASE + 0xB1)
#define REG_SCL_DMA0_59_L    (REG_SCL_DMA0_BASE + 0xB2)
#define REG_SCL_DMA0_59_H    (REG_SCL_DMA0_BASE + 0xB3)
#define REG_SCL_DMA0_5A_L    (REG_SCL_DMA0_BASE + 0xB4)
#define REG_SCL_DMA0_5A_H    (REG_SCL_DMA0_BASE + 0xB5)
#define REG_SCL_DMA0_5B_L    (REG_SCL_DMA0_BASE + 0xB6)
#define REG_SCL_DMA0_5B_H    (REG_SCL_DMA0_BASE + 0xB7)
#define REG_SCL_DMA0_5C_L    (REG_SCL_DMA0_BASE + 0xB8)
#define REG_SCL_DMA0_5C_H    (REG_SCL_DMA0_BASE + 0xB9)
#define REG_SCL_DMA0_5D_L    (REG_SCL_DMA0_BASE + 0xBA)
#define REG_SCL_DMA0_5D_H    (REG_SCL_DMA0_BASE + 0xBB)
#define REG_SCL_DMA0_5E_L    (REG_SCL_DMA0_BASE + 0xBC)
#define REG_SCL_DMA0_5E_H    (REG_SCL_DMA0_BASE + 0xBD)
#define REG_SCL_DMA0_5F_L    (REG_SCL_DMA0_BASE + 0xBE)
#define REG_SCL_DMA0_5F_H    (REG_SCL_DMA0_BASE + 0xBF)
#define REG_SCL_DMA0_60_L    (REG_SCL_DMA0_BASE + 0xC0)
#define REG_SCL_DMA0_60_H    (REG_SCL_DMA0_BASE + 0xC1)
#define REG_SCL_DMA0_61_L    (REG_SCL_DMA0_BASE + 0xC2)
#define REG_SCL_DMA0_61_H    (REG_SCL_DMA0_BASE + 0xC3)
#define REG_SCL_DMA0_62_L    (REG_SCL_DMA0_BASE + 0xC4)
#define REG_SCL_DMA0_62_H    (REG_SCL_DMA0_BASE + 0xC5)
#define REG_SCL_DMA0_63_L    (REG_SCL_DMA0_BASE + 0xC6)
#define REG_SCL_DMA0_63_H    (REG_SCL_DMA0_BASE + 0xC7)
#define REG_SCL_DMA0_64_L    (REG_SCL_DMA0_BASE + 0xC8)
#define REG_SCL_DMA0_64_H    (REG_SCL_DMA0_BASE + 0xC9)
#define REG_SCL_DMA0_65_L    (REG_SCL_DMA0_BASE + 0xCA)
#define REG_SCL_DMA0_65_H    (REG_SCL_DMA0_BASE + 0xCB)
#define REG_SCL_DMA0_66_L    (REG_SCL_DMA0_BASE + 0xCC)
#define REG_SCL_DMA0_66_H    (REG_SCL_DMA0_BASE + 0xCD)
#define REG_SCL_DMA0_67_L    (REG_SCL_DMA0_BASE + 0xCE)
#define REG_SCL_DMA0_67_H    (REG_SCL_DMA0_BASE + 0xCF)
#define REG_SCL_DMA0_68_L    (REG_SCL_DMA0_BASE + 0xD0)
#define REG_SCL_DMA0_68_H    (REG_SCL_DMA0_BASE + 0xD1)
#define REG_SCL_DMA0_69_L    (REG_SCL_DMA0_BASE + 0xD2)
#define REG_SCL_DMA0_69_H    (REG_SCL_DMA0_BASE + 0xD3)
#define REG_SCL_DMA0_6A_L    (REG_SCL_DMA0_BASE + 0xD4)
#define REG_SCL_DMA0_6A_H    (REG_SCL_DMA0_BASE + 0xD5)
#define REG_SCL_DMA0_6B_L    (REG_SCL_DMA0_BASE + 0xD6)
#define REG_SCL_DMA0_6B_H    (REG_SCL_DMA0_BASE + 0xD7)
#define REG_SCL_DMA0_6C_L    (REG_SCL_DMA0_BASE + 0xD8)
#define REG_SCL_DMA0_6C_H    (REG_SCL_DMA0_BASE + 0xD9)
#define REG_SCL_DMA0_6D_L    (REG_SCL_DMA0_BASE + 0xDA)
#define REG_SCL_DMA0_6D_H    (REG_SCL_DMA0_BASE + 0xDB)
#define REG_SCL_DMA0_6E_L    (REG_SCL_DMA0_BASE + 0xDC)
#define REG_SCL_DMA0_6E_H    (REG_SCL_DMA0_BASE + 0xDD)
#define REG_SCL_DMA0_6F_L    (REG_SCL_DMA0_BASE + 0xDE)
#define REG_SCL_DMA0_6F_H    (REG_SCL_DMA0_BASE + 0xDF)
#define REG_SCL_DMA0_70_L    (REG_SCL_DMA0_BASE + 0xE0)
#define REG_SCL_DMA0_70_H    (REG_SCL_DMA0_BASE + 0xE1)
#define REG_SCL_DMA0_71_L    (REG_SCL_DMA0_BASE + 0xE2)
#define REG_SCL_DMA0_71_H    (REG_SCL_DMA0_BASE + 0xE3)
#define REG_SCL_DMA0_72_L    (REG_SCL_DMA0_BASE + 0xE4)
#define REG_SCL_DMA0_72_H    (REG_SCL_DMA0_BASE + 0xE5)
#define REG_SCL_DMA0_73_L    (REG_SCL_DMA0_BASE + 0xE6)
#define REG_SCL_DMA0_73_H    (REG_SCL_DMA0_BASE + 0xE7)
#define REG_SCL_DMA0_74_L    (REG_SCL_DMA0_BASE + 0xE8)
#define REG_SCL_DMA0_74_H    (REG_SCL_DMA0_BASE + 0xE9)
#define REG_SCL_DMA0_75_L    (REG_SCL_DMA0_BASE + 0xEA)
#define REG_SCL_DMA0_75_H    (REG_SCL_DMA0_BASE + 0xEB)
#define REG_SCL_DMA0_76_L    (REG_SCL_DMA0_BASE + 0xEC)
#define REG_SCL_DMA0_76_H    (REG_SCL_DMA0_BASE + 0xED)
#define REG_SCL_DMA0_77_L    (REG_SCL_DMA0_BASE + 0xEE)
#define REG_SCL_DMA0_77_H    (REG_SCL_DMA0_BASE + 0xEF)
#define REG_SCL_DMA0_78_L    (REG_SCL_DMA0_BASE + 0xF0)
#define REG_SCL_DMA0_78_H    (REG_SCL_DMA0_BASE + 0xF1)
#define REG_SCL_DMA0_79_L    (REG_SCL_DMA0_BASE + 0xF2)
#define REG_SCL_DMA0_79_H    (REG_SCL_DMA0_BASE + 0xF3)
#define REG_SCL_DMA0_7A_L    (REG_SCL_DMA0_BASE + 0xF4)
#define REG_SCL_DMA0_7A_H    (REG_SCL_DMA0_BASE + 0xF5)
#define REG_SCL_DMA0_7B_L    (REG_SCL_DMA0_BASE + 0xF6)
#define REG_SCL_DMA0_7B_H    (REG_SCL_DMA0_BASE + 0xF7)
#define REG_SCL_DMA0_7C_L    (REG_SCL_DMA0_BASE + 0xF8)
#define REG_SCL_DMA0_7C_H    (REG_SCL_DMA0_BASE + 0xF9)
#define REG_SCL_DMA0_7D_L    (REG_SCL_DMA0_BASE + 0xFA)
#define REG_SCL_DMA0_7D_H    (REG_SCL_DMA0_BASE + 0xFB)
#define REG_SCL_DMA0_7E_L    (REG_SCL_DMA0_BASE + 0xFC)
#define REG_SCL_DMA0_7E_H    (REG_SCL_DMA0_BASE + 0xFD)
#define REG_SCL_DMA0_7F_L    (REG_SCL_DMA0_BASE + 0xFE)
#define REG_SCL_DMA0_7F_H    (REG_SCL_DMA0_BASE + 0xFF)

#define REG_SCL0_00_L        (REG_SCL0_BASE + 0x00)
#define REG_SCL0_00_H        (REG_SCL0_BASE + 0x01)
#define REG_SCL0_01_L        (REG_SCL0_BASE + 0x02)
#define REG_SCL0_01_H        (REG_SCL0_BASE + 0x03)
#define REG_SCL0_02_L        (REG_SCL0_BASE + 0x04)
#define REG_SCL0_02_H        (REG_SCL0_BASE + 0x05)
#define REG_SCL0_03_L        (REG_SCL0_BASE + 0x06)
#define REG_SCL0_03_H        (REG_SCL0_BASE + 0x07)
#define REG_SCL0_04_L        (REG_SCL0_BASE + 0x08)
#define REG_SCL0_04_H        (REG_SCL0_BASE + 0x09)
#define REG_SCL0_05_L        (REG_SCL0_BASE + 0x0A)
#define REG_SCL0_05_H        (REG_SCL0_BASE + 0x0B)
#define REG_SCL0_06_L        (REG_SCL0_BASE + 0x0C)
#define REG_SCL0_06_H        (REG_SCL0_BASE + 0x0D)
#define REG_SCL0_07_L        (REG_SCL0_BASE + 0x0E)
#define REG_SCL0_07_H        (REG_SCL0_BASE + 0x0F)
#define REG_SCL0_08_L        (REG_SCL0_BASE + 0x10)
#define REG_SCL0_08_H        (REG_SCL0_BASE + 0x11)
#define REG_SCL0_09_L        (REG_SCL0_BASE + 0x12)
#define REG_SCL0_09_H        (REG_SCL0_BASE + 0x13)
#define REG_SCL0_0A_L        (REG_SCL0_BASE + 0x14)
#define REG_SCL0_0A_H        (REG_SCL0_BASE + 0x15)
#define REG_SCL0_0B_L        (REG_SCL0_BASE + 0x16)
#define REG_SCL0_0B_H        (REG_SCL0_BASE + 0x17)
#define REG_SCL0_0C_L        (REG_SCL0_BASE + 0x18)
#define REG_SCL0_0C_H        (REG_SCL0_BASE + 0x19)
#define REG_SCL0_0D_L        (REG_SCL0_BASE + 0x1A)
#define REG_SCL0_0D_H        (REG_SCL0_BASE + 0x1B)
#define REG_SCL0_0E_L        (REG_SCL0_BASE + 0x1C)
#define REG_SCL0_0E_H        (REG_SCL0_BASE + 0x1D)
#define REG_SCL0_0F_L        (REG_SCL0_BASE + 0x1E)
#define REG_SCL0_0F_H        (REG_SCL0_BASE + 0x1F)
#define REG_SCL0_10_L        (REG_SCL0_BASE + 0x20)
#define REG_SCL0_10_H        (REG_SCL0_BASE + 0x21)
#define REG_SCL0_11_L        (REG_SCL0_BASE + 0x22)
#define REG_SCL0_11_H        (REG_SCL0_BASE + 0x23)
#define REG_SCL0_12_L        (REG_SCL0_BASE + 0x24)
#define REG_SCL0_12_H        (REG_SCL0_BASE + 0x25)
#define REG_SCL0_13_L        (REG_SCL0_BASE + 0x26)
#define REG_SCL0_13_H        (REG_SCL0_BASE + 0x27)
#define REG_SCL0_14_L        (REG_SCL0_BASE + 0x28)
#define REG_SCL0_14_H        (REG_SCL0_BASE + 0x29)
#define REG_SCL0_15_L        (REG_SCL0_BASE + 0x2A)
#define REG_SCL0_15_H        (REG_SCL0_BASE + 0x2B)
#define REG_SCL0_16_L        (REG_SCL0_BASE + 0x2C)
#define REG_SCL0_16_H        (REG_SCL0_BASE + 0x2D)
#define REG_SCL0_17_L        (REG_SCL0_BASE + 0x2E)
#define REG_SCL0_17_H        (REG_SCL0_BASE + 0x2F)
#define REG_SCL0_18_L        (REG_SCL0_BASE + 0x30)
#define REG_SCL0_18_H        (REG_SCL0_BASE + 0x31)
#define REG_SCL0_19_L        (REG_SCL0_BASE + 0x32)
#define REG_SCL0_19_H        (REG_SCL0_BASE + 0x33)
#define REG_SCL0_1A_L        (REG_SCL0_BASE + 0x34)
#define REG_SCL0_1A_H        (REG_SCL0_BASE + 0x35)
#define REG_SCL0_1B_L        (REG_SCL0_BASE + 0x36)
#define REG_SCL0_1B_H        (REG_SCL0_BASE + 0x37)
#define REG_SCL0_1C_L        (REG_SCL0_BASE + 0x38)
#define REG_SCL0_1C_H        (REG_SCL0_BASE + 0x39)
#define REG_SCL0_1D_L        (REG_SCL0_BASE + 0x3A)
#define REG_SCL0_1D_H        (REG_SCL0_BASE + 0x3B)
#define REG_SCL0_1E_L        (REG_SCL0_BASE + 0x3C)
#define REG_SCL0_1E_H        (REG_SCL0_BASE + 0x3D)
#define REG_SCL0_1F_L        (REG_SCL0_BASE + 0x3E)
#define REG_SCL0_1F_H        (REG_SCL0_BASE + 0x3F)
#define REG_SCL0_20_L        (REG_SCL0_BASE + 0x40)
#define REG_SCL0_20_H        (REG_SCL0_BASE + 0x41)
#define REG_SCL0_21_L        (REG_SCL0_BASE + 0x42)
#define REG_SCL0_21_H        (REG_SCL0_BASE + 0x43)
#define REG_SCL0_22_L        (REG_SCL0_BASE + 0x44)
#define REG_SCL0_22_H        (REG_SCL0_BASE + 0x45)
#define REG_SCL0_23_L        (REG_SCL0_BASE + 0x46)
#define REG_SCL0_23_H        (REG_SCL0_BASE + 0x47)
#define REG_SCL0_24_L        (REG_SCL0_BASE + 0x48)
#define REG_SCL0_24_H        (REG_SCL0_BASE + 0x49)
#define REG_SCL0_25_L        (REG_SCL0_BASE + 0x4A)
#define REG_SCL0_25_H        (REG_SCL0_BASE + 0x4B)
#define REG_SCL0_26_L        (REG_SCL0_BASE + 0x4C)
#define REG_SCL0_26_H        (REG_SCL0_BASE + 0x4D)
#define REG_SCL0_27_L        (REG_SCL0_BASE + 0x4E)
#define REG_SCL0_27_H        (REG_SCL0_BASE + 0x4F)
#define REG_SCL0_28_L        (REG_SCL0_BASE + 0x50)
#define REG_SCL0_28_H        (REG_SCL0_BASE + 0x51)
#define REG_SCL0_29_L        (REG_SCL0_BASE + 0x52)
#define REG_SCL0_29_H        (REG_SCL0_BASE + 0x53)
#define REG_SCL0_2A_L        (REG_SCL0_BASE + 0x54)
#define REG_SCL0_2A_H        (REG_SCL0_BASE + 0x55)
#define REG_SCL0_2B_L        (REG_SCL0_BASE + 0x56)
#define REG_SCL0_2B_H        (REG_SCL0_BASE + 0x57)
#define REG_SCL0_2C_L        (REG_SCL0_BASE + 0x58)
#define REG_SCL0_2C_H        (REG_SCL0_BASE + 0x59)
#define REG_SCL0_2D_L        (REG_SCL0_BASE + 0x5A)
#define REG_SCL0_2D_H        (REG_SCL0_BASE + 0x5B)
#define REG_SCL0_2E_L        (REG_SCL0_BASE + 0x5C)
#define REG_SCL0_2E_H        (REG_SCL0_BASE + 0x5D)
#define REG_SCL0_2F_L        (REG_SCL0_BASE + 0x5E)
#define REG_SCL0_2F_H        (REG_SCL0_BASE + 0x5F)
#define REG_SCL0_30_L        (REG_SCL0_BASE + 0x60)
#define REG_SCL0_30_H        (REG_SCL0_BASE + 0x61)
#define REG_SCL0_31_L        (REG_SCL0_BASE + 0x62)
#define REG_SCL0_31_H        (REG_SCL0_BASE + 0x63)
#define REG_SCL0_32_L        (REG_SCL0_BASE + 0x64)
#define REG_SCL0_32_H        (REG_SCL0_BASE + 0x65)
#define REG_SCL0_33_L        (REG_SCL0_BASE + 0x66)
#define REG_SCL0_33_H        (REG_SCL0_BASE + 0x67)
#define REG_SCL0_34_L        (REG_SCL0_BASE + 0x68)
#define REG_SCL0_34_H        (REG_SCL0_BASE + 0x69)
#define REG_SCL0_35_L        (REG_SCL0_BASE + 0x6A)
#define REG_SCL0_35_H        (REG_SCL0_BASE + 0x6B)
#define REG_SCL0_36_L        (REG_SCL0_BASE + 0x6C)
#define REG_SCL0_36_H        (REG_SCL0_BASE + 0x6D)
#define REG_SCL0_37_L        (REG_SCL0_BASE + 0x6E)
#define REG_SCL0_37_H        (REG_SCL0_BASE + 0x6F)
#define REG_SCL0_38_L        (REG_SCL0_BASE + 0x70)
#define REG_SCL0_38_H        (REG_SCL0_BASE + 0x71)
#define REG_SCL0_39_L        (REG_SCL0_BASE + 0x72)
#define REG_SCL0_39_H        (REG_SCL0_BASE + 0x73)
#define REG_SCL0_3A_L        (REG_SCL0_BASE + 0x74)
#define REG_SCL0_3A_H        (REG_SCL0_BASE + 0x75)
#define REG_SCL0_3B_L        (REG_SCL0_BASE + 0x76)
#define REG_SCL0_3B_H        (REG_SCL0_BASE + 0x77)
#define REG_SCL0_3C_L        (REG_SCL0_BASE + 0x78)
#define REG_SCL0_3C_H        (REG_SCL0_BASE + 0x79)
#define REG_SCL0_3D_L        (REG_SCL0_BASE + 0x7A)
#define REG_SCL0_3D_H        (REG_SCL0_BASE + 0x7B)
#define REG_SCL0_3E_L        (REG_SCL0_BASE + 0x7C)
#define REG_SCL0_3E_H        (REG_SCL0_BASE + 0x7D)
#define REG_SCL0_3F_L        (REG_SCL0_BASE + 0x7E)
#define REG_SCL0_3F_H        (REG_SCL0_BASE + 0x7F)
#define REG_SCL0_40_L        (REG_SCL0_BASE + 0x80)
#define REG_SCL0_40_H        (REG_SCL0_BASE + 0x81)
#define REG_SCL0_41_L        (REG_SCL0_BASE + 0x82)
#define REG_SCL0_41_H        (REG_SCL0_BASE + 0x83)
#define REG_SCL0_42_L        (REG_SCL0_BASE + 0x84)
#define REG_SCL0_42_H        (REG_SCL0_BASE + 0x85)
#define REG_SCL0_43_L        (REG_SCL0_BASE + 0x86)
#define REG_SCL0_43_H        (REG_SCL0_BASE + 0x87)
#define REG_SCL0_44_L        (REG_SCL0_BASE + 0x88)
#define REG_SCL0_44_H        (REG_SCL0_BASE + 0x89)
#define REG_SCL0_45_L        (REG_SCL0_BASE + 0x8A)
#define REG_SCL0_45_H        (REG_SCL0_BASE + 0x8B)
#define REG_SCL0_46_L        (REG_SCL0_BASE + 0x8C)
#define REG_SCL0_46_H        (REG_SCL0_BASE + 0x8D)
#define REG_SCL0_47_L        (REG_SCL0_BASE + 0x8E)
#define REG_SCL0_47_H        (REG_SCL0_BASE + 0x8F)
#define REG_SCL0_48_L        (REG_SCL0_BASE + 0x90)
#define REG_SCL0_48_H        (REG_SCL0_BASE + 0x91)
#define REG_SCL0_49_L        (REG_SCL0_BASE + 0x92)
#define REG_SCL0_49_H        (REG_SCL0_BASE + 0x93)
#define REG_SCL0_4A_L        (REG_SCL0_BASE + 0x94)
#define REG_SCL0_4A_H        (REG_SCL0_BASE + 0x95)
#define REG_SCL0_4B_L        (REG_SCL0_BASE + 0x96)
#define REG_SCL0_4B_H        (REG_SCL0_BASE + 0x97)
#define REG_SCL0_4C_L        (REG_SCL0_BASE + 0x98)
#define REG_SCL0_4C_H        (REG_SCL0_BASE + 0x99)
#define REG_SCL0_4D_L        (REG_SCL0_BASE + 0x9A)
#define REG_SCL0_4D_H        (REG_SCL0_BASE + 0x9B)
#define REG_SCL0_4E_L        (REG_SCL0_BASE + 0x9C)
#define REG_SCL0_4E_H        (REG_SCL0_BASE + 0x9D)
#define REG_SCL0_4F_L        (REG_SCL0_BASE + 0x9E)
#define REG_SCL0_4F_H        (REG_SCL0_BASE + 0x9F)
#define REG_SCL0_50_L        (REG_SCL0_BASE + 0xA0)
#define REG_SCL0_50_H        (REG_SCL0_BASE + 0xA1)
#define REG_SCL0_51_L        (REG_SCL0_BASE + 0xA2)
#define REG_SCL0_51_H        (REG_SCL0_BASE + 0xA3)
#define REG_SCL0_52_L        (REG_SCL0_BASE + 0xA4)
#define REG_SCL0_52_H        (REG_SCL0_BASE + 0xA5)
#define REG_SCL0_53_L        (REG_SCL0_BASE + 0xA6)
#define REG_SCL0_53_H        (REG_SCL0_BASE + 0xA7)
#define REG_SCL0_54_L        (REG_SCL0_BASE + 0xA8)
#define REG_SCL0_54_H        (REG_SCL0_BASE + 0xA9)
#define REG_SCL0_55_L        (REG_SCL0_BASE + 0xAA)
#define REG_SCL0_55_H        (REG_SCL0_BASE + 0xAB)
#define REG_SCL0_56_L        (REG_SCL0_BASE + 0xAC)
#define REG_SCL0_56_H        (REG_SCL0_BASE + 0xAD)
#define REG_SCL0_57_L        (REG_SCL0_BASE + 0xAE)
#define REG_SCL0_57_H        (REG_SCL0_BASE + 0xAF)
#define REG_SCL0_58_L        (REG_SCL0_BASE + 0xB0)
#define REG_SCL0_58_H        (REG_SCL0_BASE + 0xB1)
#define REG_SCL0_59_L        (REG_SCL0_BASE + 0xB2)
#define REG_SCL0_59_H        (REG_SCL0_BASE + 0xB3)
#define REG_SCL0_5A_L        (REG_SCL0_BASE + 0xB4)
#define REG_SCL0_5A_H        (REG_SCL0_BASE + 0xB5)
#define REG_SCL0_5B_L        (REG_SCL0_BASE + 0xB6)
#define REG_SCL0_5B_H        (REG_SCL0_BASE + 0xB7)
#define REG_SCL0_5C_L        (REG_SCL0_BASE + 0xB8)
#define REG_SCL0_5C_H        (REG_SCL0_BASE + 0xB9)
#define REG_SCL0_5D_L        (REG_SCL0_BASE + 0xBA)
#define REG_SCL0_5D_H        (REG_SCL0_BASE + 0xBB)
#define REG_SCL0_5E_L        (REG_SCL0_BASE + 0xBC)
#define REG_SCL0_5E_H        (REG_SCL0_BASE + 0xBD)
#define REG_SCL0_5F_L        (REG_SCL0_BASE + 0xBE)
#define REG_SCL0_5F_H        (REG_SCL0_BASE + 0xBF)
#define REG_SCL0_60_L        (REG_SCL0_BASE + 0xC0)
#define REG_SCL0_60_H        (REG_SCL0_BASE + 0xC1)
#define REG_SCL0_61_L        (REG_SCL0_BASE + 0xC2)
#define REG_SCL0_61_H        (REG_SCL0_BASE + 0xC3)
#define REG_SCL0_62_L        (REG_SCL0_BASE + 0xC4)
#define REG_SCL0_62_H        (REG_SCL0_BASE + 0xC5)
#define REG_SCL0_63_L        (REG_SCL0_BASE + 0xC6)
#define REG_SCL0_63_H        (REG_SCL0_BASE + 0xC7)
#define REG_SCL0_64_L        (REG_SCL0_BASE + 0xC8)
#define REG_SCL0_64_H        (REG_SCL0_BASE + 0xC9)
#define REG_SCL0_65_L        (REG_SCL0_BASE + 0xCA)
#define REG_SCL0_65_H        (REG_SCL0_BASE + 0xCB)
#define REG_SCL0_66_L        (REG_SCL0_BASE + 0xCC)
#define REG_SCL0_66_H        (REG_SCL0_BASE + 0xCD)
#define REG_SCL0_67_L        (REG_SCL0_BASE + 0xCE)
#define REG_SCL0_67_H        (REG_SCL0_BASE + 0xCF)
#define REG_SCL0_68_L        (REG_SCL0_BASE + 0xD0)
#define REG_SCL0_68_H        (REG_SCL0_BASE + 0xD1)
#define REG_SCL0_69_L        (REG_SCL0_BASE + 0xD2)
#define REG_SCL0_69_H        (REG_SCL0_BASE + 0xD3)
#define REG_SCL0_6A_L        (REG_SCL0_BASE + 0xD4)
#define REG_SCL0_6A_H        (REG_SCL0_BASE + 0xD5)
#define REG_SCL0_6B_L        (REG_SCL0_BASE + 0xD6)
#define REG_SCL0_6B_H        (REG_SCL0_BASE + 0xD7)
#define REG_SCL0_6C_L        (REG_SCL0_BASE + 0xD8)
#define REG_SCL0_6C_H        (REG_SCL0_BASE + 0xD9)
#define REG_SCL0_6D_L        (REG_SCL0_BASE + 0xDA)
#define REG_SCL0_6D_H        (REG_SCL0_BASE + 0xDB)
#define REG_SCL0_6E_L        (REG_SCL0_BASE + 0xDC)
#define REG_SCL0_6E_H        (REG_SCL0_BASE + 0xDD)
#define REG_SCL0_6F_L        (REG_SCL0_BASE + 0xDE)
#define REG_SCL0_6F_H        (REG_SCL0_BASE + 0xDF)
#define REG_SCL0_70_L        (REG_SCL0_BASE + 0xE0)
#define REG_SCL0_70_H        (REG_SCL0_BASE + 0xE1)
#define REG_SCL0_71_L        (REG_SCL0_BASE + 0xE2)
#define REG_SCL0_71_H        (REG_SCL0_BASE + 0xE3)
#define REG_SCL0_72_L        (REG_SCL0_BASE + 0xE4)
#define REG_SCL0_72_H        (REG_SCL0_BASE + 0xE5)
#define REG_SCL0_73_L        (REG_SCL0_BASE + 0xE6)
#define REG_SCL0_73_H        (REG_SCL0_BASE + 0xE7)
#define REG_SCL0_74_L        (REG_SCL0_BASE + 0xE8)
#define REG_SCL0_74_H        (REG_SCL0_BASE + 0xE9)
#define REG_SCL0_75_L        (REG_SCL0_BASE + 0xEA)
#define REG_SCL0_75_H        (REG_SCL0_BASE + 0xEB)
#define REG_SCL0_76_L        (REG_SCL0_BASE + 0xEC)
#define REG_SCL0_76_H        (REG_SCL0_BASE + 0xED)
#define REG_SCL0_77_L        (REG_SCL0_BASE + 0xEE)
#define REG_SCL0_77_H        (REG_SCL0_BASE + 0xEF)
#define REG_SCL0_78_L        (REG_SCL0_BASE + 0xF0)
#define REG_SCL0_78_H        (REG_SCL0_BASE + 0xF1)
#define REG_SCL0_79_L        (REG_SCL0_BASE + 0xF2)
#define REG_SCL0_79_H        (REG_SCL0_BASE + 0xF3)
#define REG_SCL0_7A_L        (REG_SCL0_BASE + 0xF4)
#define REG_SCL0_7A_H        (REG_SCL0_BASE + 0xF5)
#define REG_SCL0_7B_L        (REG_SCL0_BASE + 0xF6)
#define REG_SCL0_7B_H        (REG_SCL0_BASE + 0xF7)
#define REG_SCL0_7C_L        (REG_SCL0_BASE + 0xF8)
#define REG_SCL0_7C_H        (REG_SCL0_BASE + 0xF9)
#define REG_SCL0_7D_L        (REG_SCL0_BASE + 0xFA)
#define REG_SCL0_7D_H        (REG_SCL0_BASE + 0xFB)
#define REG_SCL0_7E_L        (REG_SCL0_BASE + 0xFC)
#define REG_SCL0_7E_H        (REG_SCL0_BASE + 0xFD)
#define REG_SCL0_7F_L        (REG_SCL0_BASE + 0xFE)
#define REG_SCL0_7F_H        (REG_SCL0_BASE + 0xFF)

#endif /* __HAL_DISP_REG_H__ */
