/*
* gpio.h- Sigmastar
*
* Copyright (C) 2018 Sigmastar Technology Corp.
*
* Author: giggshuang <giggshuang@sigmastar.com.tw>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
*/

#ifndef __GPIO_H__
#define __GPIO_H__

#define PAD_GPIO0           0
#define PAD_GPIO1           1
#define PAD_GPIO2           2
#define PAD_GPIO3           3
#define PAD_GPIO4           4
#define PAD_GPIO5           5
#define PAD_GPIO6           6
#define PAD_GPIO7           7
#define PAD_GPIO8           8
#define PAD_GPIO9           9
#define PAD_GPIO10          10
#define PAD_GPIO11          11
#define PAD_GPIO12          12
#define PAD_GPIO13          13
#define PAD_GPIO14          14
#define PAD_GPIO15          15
#define PAD_FUART_RX        16
#define PAD_FUART_TX        17
#define PAD_FUART_CTS       18
#define PAD_FUART_RTS       19
#define PAD_I2C0_SCL        20
#define PAD_I2C0_SDA        21
#define PAD_I2C1_SCL        22
#define PAD_I2C1_SDA        23
#define PAD_SR_IO00         24
#define PAD_SR_IO01         25
#define PAD_SR_IO02         26
#define PAD_SR_IO03         27
#define PAD_SR_IO04         28
#define PAD_SR_IO05         29
#define PAD_SR_IO06         30
#define PAD_SR_IO07         31
#define PAD_SR_IO08         32
#define PAD_SR_IO09         33
#define PAD_SR_IO10         34
#define PAD_SR_IO11         35
#define PAD_SR_IO12         36
#define PAD_SR_IO13         37
#define PAD_SR_IO14         38
#define PAD_SR_IO15         39
#define PAD_SR_IO16         40
#define PAD_SR_IO17         41
#define PAD_NAND_ALE        42
#define PAD_NAND_CLE        43
#define PAD_NAND_CEZ        44
#define PAD_NAND_WEZ        45
#define PAD_NAND_WPZ        46
#define PAD_NAND_REZ        47
#define PAD_NAND_RBZ        48
#define PAD_NAND_DA0        49
#define PAD_NAND_DA1        50
#define PAD_NAND_DA2        51
#define PAD_NAND_DA3        52
#define PAD_NAND_DA4        53
#define PAD_NAND_DA5        54
#define PAD_NAND_DA6        55
#define PAD_NAND_DA7        56
#define PAD_UART0_RX        57
#define PAD_UART0_TX        58
#define PAD_UART1_RX        59
#define PAD_UART1_TX        60
#define PAD_SPI0_CZ         61
#define PAD_SPI0_CK         62
#define PAD_SPI0_DI         63
#define PAD_SPI0_DO         64
#define PAD_SPI1_CZ         65
#define PAD_SPI1_CK         66
#define PAD_SPI1_DI         67
#define PAD_SPI1_DO         68
#define PAD_PWM0            69
#define PAD_PWM1            70
#define PAD_SD_CLK          71
#define PAD_SD_CMD          72
#define PAD_SD_D0           73
#define PAD_SD_D1           74
#define PAD_SD_D2           75
#define PAD_SD_D3           76
#define PAD_PM_SD_CDZ       77
#define PAD_PM_IRIN         78
#define PAD_PM_GPIO0        79
#define PAD_PM_GPIO1        80
#define PAD_PM_GPIO2        81
#define PAD_PM_GPIO3        82
#define PAD_PM_GPIO4        83
#define PAD_PM_GPIO5        84
#define PAD_PM_GPIO6        85
#define PAD_PM_GPIO7        86
#define PAD_PM_GPIO8        87
#define PAD_PM_GPIO9        88
#define PAD_PM_GPIO10       89
#define PAD_PM_SPI_CZ       90
#define PAD_PM_SPI_CK       91
#define PAD_PM_SPI_DI       92
#define PAD_PM_SPI_DO       93
#define PAD_PM_SPI_WPZ      94
#define PAD_PM_SPI_HLD      95
#define PAD_PM_LED0         96
#define PAD_PM_LED1         97
#define PAD_SAR_GPIO0       98
#define PAD_SAR_GPIO1       99
#define PAD_SAR_GPIO2       100
#define PAD_SAR_GPIO3       101
#define PAD_ETH_RN          102
#define PAD_ETH_RP          103
#define PAD_ETH_TN          104
#define PAD_ETH_TP          105
#define PAD_USB_DM          106
#define PAD_USB_DP          107
#define PAD_DM_P1           108
#define PAD_DP_P1           109

#define GPIO_NR             110

#endif  // __GPIO_H__
